I know from the datasheet that it gets set automatically on a rising edge of the WR bit and cleared automatically on a successful completion. Thus, if it's still on, then something went wrong. So far so good, but how closely should I watch it?
The chip that I'm using for this project (PIC16F1454) erases and writes its program memory in "rows" of 32 words each. A write to this memory actually goes to one of 32 transparent latches that corresponds to the lower bits of the address. Then, if the LWLO bit is off, the same operation then transfers all 32 latches simultaneously to the row specified by the upper bits. So the procedure, given a memory image, is to erase a row if it isn't already, set LWLO, fill the row except for the last word, clear LWLO, and write the last word.
During this process, I'm setting WR for each word as part of writing the latch, so WRERR should be on also. Then if the write is successful, WRERR turns back off again. The datasheet doesn't say if the latch has the success rate of ordinary RAM or what to do if it goes wrong. It does say that the latches are all reset to the erased value (0x3FFF) after being transferred. Is it a problem to blindly fill the row and transfer it, then check WRERR and repeat the row if necessary? If WRERR is good, then I'll verify the data itself and repeat if necessary.
In other words, is it possible to fail when writing a latch only?