I've designed a few PCB's now, but never put much thought into good practices. They were small boards and most of the emphasis was put into just making sure everything that needed to be connected was connected.

Now I want to get more serious into making well designed boards. I've designed and redesigned my current project multiple times trying to come up with a good looking layout.

This project is based around the ATXMega256 mCU running on a 16Mhz crystal, around 60 total components and 7 or 8 of them being IC's.

For my next redesign, I plan on giving "Manhattan Routing" a go to at least try and help with crazy traces going every which way - but that's a little bit off topic.

The problem I seem to run into the most is understanding an appropriate method of running power to each IC. Normally, I would just daisy chain them but that is said to be a bad practice.

Here are my questions relating to feeding power

  1. I've heard of the "Star Configuration" where all the IC's tie directly into the regulator but haven't seen a real life example of that so I'm not sure how to design that into my projects. It sounds like a mess of traces coming off of one pad in my mind. Can you post an example of a well designed Star Configuration?

  2. What would be some advantages and disadvantages of using the star configuration as opposed to a power plane, other than the obvious of power being everywhere with a plane.

  3. When is it ok or not ok to use a plane for VCC, specifically for a 2 layer board as I've heard that it's not as common on a 2 layer board?

  4. If I shouldn't use a power plane, which is better in the case of traces needing to cross each other: using via's for GPIO or via's for power?

  5. If it is ok to use a power plane on a 2 layer board, should VCC be on the top layer or bottom, obviously I would have a Ground plane as well.

I know there isn't a win/win answer to these questions because every project is going to be different and require different planning, but I think the basic concept behind it should be somewhat universal that people follow. You have to know the rules before you can break them.

I also realize that these questions may be beyond the scope of online discussion, but I'm looking for more general answers that can help push me in the right direction.

  • \$\begingroup\$ I think this is a good question overall, but it might be a little broad because it has several questions in one (isn't focused enough on one specific thing). \$\endgroup\$ – JYelton Sep 17 '14 at 17:31

I'd recommend looking at PCB Design Guidelines For Reduced EMI by Texas Instruments.

While it is focused on reducing EMI, it offers advice or answers to all of your questions except "Manhattan Routing".

Section 2.1 (about 12 pages) is about Ground and power. It includes these useful sections:

2.1.7 Power Plane Do’s and Don’ts for Four-Layer Boards
2.2.1 Single-Point vs Multipoint Distribution
2.2.2 Star Distribution
2.2.3 Gridding to Create Planes

It shows how to get close to 4-layer PCB EMI performance using a 2-layer board. Part of reducing EMI is to ensure there is good power and ground routing and decoupling.

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    \$\begingroup\$ @Jonas Wielicki - Thank you for your improvements, you motivated me to be more clear and specific. \$\endgroup\$ – gbulmer Sep 17 '14 at 19:21

This isn't strictly an answer - I don't know if there really is a definitive answer, or just people's opinions. It's too long for a comment though, so sue me.

As I said, this isn't really an answer, it's just how I do my layout and routing - I don't know how "right" it is, or how "proper", but it Works For Me™.

Manhattan routing, while nice, isn't always the answer. I use a kind of hybrid Manhattan - a lot of the time it's up/down and left/right, but not always - it depends on the exact situation. I place via reduction over trace direction - if I can do a little up/down on the left/right plane and remove the need for 2 vias then I will.

As for power - I tend to use loops and semi-star. Think of it as a star with loops on the end. Especially when one chip has maybe 5 or 6 power pins, the chip's power trace would form a loop around all the pins and back to the beginning. The same with groups of chips. They don't always go right back to the regulator / power circuit, but they do go back to a lower impedance "trunk" trace that then goes back to the regulator.

Vias on power or IO? Well, it depends on the power, and the IO. Vias introduce increased inductance and resistance. Too many vias on power can cause excess voltage drop, or reduce current handling capability. Too many vias on IO can reduce the maximum clock speeds and data rates you can work with, and also increase EMI emissions. In general though I tend to prefer to keep the vias on power to an absolute minimum. To that end I usually lay out the power traces first before anything else.

If you must have a power plane on a 2 layer board (I for one never do - ground planes, yes, but not power planes) I think it's best to have it on the top. Chiefly because the ground plane, which would then be on the bottom, would normally be adjacent to the chassis - and if that's metal and grounded then the ground is next to the ground and can't cause any nasty shorts. Power next to ground could cause shorts.

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    \$\begingroup\$ This is a really long comment! Legal papers have been mailed to you. :) \$\endgroup\$ – JYelton Sep 17 '14 at 18:00
  • \$\begingroup\$ On the Manhattan routing, right, I wont follow it that strictly when I can save from using vias, but for longer runs I think it should give the board a nice "shine". \$\endgroup\$ – bwoogie Sep 17 '14 at 18:06
  • \$\begingroup\$ I think I understand your explanation of using the Star Configuration. Would you mind posting a picture of it in practice? I'm quite the learn by visual kind of person. \$\endgroup\$ – bwoogie Sep 17 '14 at 18:07
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    \$\begingroup\$ let's say your regulator is near the input jack to the PCB, with all your nice big fat capacitors and TVS diodes etc (you DO have them right?! and a fuse!) well if you need to distribute power (regulated, 5V let's say) then it would be partially "star-like" to have two large fat 2mm power traces go down each side of the PCB towards the opposite end, and smaller branches come off and go to the individual ICs. The smaller branches would each have their own local decoupling capacitors for each of their ICs too. This helps in power transients. \$\endgroup\$ – KyranF Sep 17 '14 at 18:23

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