That link you gave says it all:
Hint: - 2’s complement of a number can
be obtained by keeping the least
significant bits as such until the
first 1, and then complementing all
bits
"example 001010 → 110110" that is to say
001010 -> flip bits -> 110101 -> add 1 -> 110110
msb lsb msb lsb msb lsb
msb lsb
input 001010
output 110110
<--- time
So there are two states - "I haven't seen a one yet" and "I have seen a one previously". Given my state and my current input, my output and next state are fully determined.
If my current state is "I haven't seen a one yet" and my input is a 0, my output is a 0 and my next state is (still) "I haven't seen a one yet"
If my current state is "I haven't seen a one yet" and my input is a 1, my output is a 1 and my next state is (changes to) "I have seen a one previously"
If my current state is "I have seen a one previously" and my input is a 0, my output is a 1 and my next state is (still) "I have seen a one previously"
If my current state is "I have seen a one previously" and my input is a 1, my output is a 0 and my next state is (still) "I have seen a one previously"
Write that out as a truth table encoding "I haven't seen a one yet" as 0 and "I have seen a one previously" as 1, and you should be home free.
To "wire it up" the current data input bit and the current state go into logic that feeds the input to the D-flip flop and separate logic that feeds the input to the shift register, the D-flip-flop holds the "state variable", and both are clocked by the data clock. And to be complete you need some kind of reset logic - left as an exercise to the reader. The "current state" is the output of the D-flip-flop, and next state is the input to it...
+----------------------------+
| |
| +---------+ +-----+ |
+--+ Logic A +-----+ DFF +---+
Data-+-|--+ | | |
| | +---------+ | CLK |
| | +--+--+
| | |
| | +--------Clock
| | +--+--+
| | +---------+ | CLK |
| +--+ Logic B +-----+ |
+----+ | | S R |
+---------+ +-----+