My book says the following:
As noted previously, every method of circuit analysis must satisfy KVL, KCL, and the device i–v relationships. In developing the node-voltage equations in Eqs. (3–4), it may appear that we have not used KVL. However, KVL is satisfied because the equations \$v_1 = v_1\$, \$v_2=v_A-v_B\$, and \$v_3=v_B\$ were used to write the right side of the element equations in Eqs. (3–3). The KVL constraints do not appear explicitly in the formulation of node equations, but they are implicitly included when the fundamental property of node analysis is used to write the element voltages in terms of the node voltages.
I don't see why this is part of the above excerpt is true:
The KVL constraints do not appear explicitly in the formulation of node equations, but they are implicitly included when the fundamental property of node analysis is used to write the element voltages in terms of the node voltages.
How is KVL used to write the element voltages in terms of the node voltages? Note that I'm not asking how to write the element voltages in terms of the node voltages. I'm asking why the author claims KVL plays a role in this.