rd=1; case1=2 ; i=2; n1=23; always @(posedge clka) begin counter=counter+1; if (rd==1) begin #5 window[i]<=douta; ~~~~~~~~~~~ Statement1 case(i) case1: addra=n1; case2: addra= n2; endcase #5 addra<=addra+1; ~~~~~~~~~~~Statement2 #5 i<=i+1; end end
The statement inside always block in verilog is sequential. At the positive edge of clock :
counter=counter+1 if (rd==1) (true)
Confusion: My confusion is that as case statement is occur first because window[i]=douta (after 5 unit time). After this statement 2 occur or statement 1 and statement occur at same time.
Please anyone clear my doubt after how statement inside always block in this case run. Thank you