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We are using the ADuM1301 digital isolator in one of our designs. The PCB layout section from the data sheet states:

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In applications involving high common-mode transients, care should be taken to ensure that board coupling across the isolation barrier is minimized. Furthermore, the board layout should be designed such that any coupling that does occur equally affects all pins on a given component side. Failure to ensure this could cause voltage differentials between pins exceeding the absolute maximum ratings of the device, thereby leading to latch-up or permanent damage.

Preventing coupling across the isolation barrier sounds logical. However, what do they mean with "the board layout should be designed such that any coupling that does occur equally affects all pins on a given component side"? If I apply a ESD pulse to one of the signals, how would I prevent "voltage differentials between pins exceeding the absolute maximum ratings" by following these guideline?

EDIT: I forgot to mention that we actually experience reproducible latch up on one existing design (which sadly does not follow any design guideline of the ADUM at all). Now I would like to get it right for redesign.

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Keep the layout symmetrical so that there isn't much difference in coupling. We're talking about common mode signals which means that a large difference in voltage is appearing across the isolation barrier. If one of the pins is coupled better to the CM transient then a normal mode voltage appears. I would also include coupling to ground in this thinking, since a (say) 1KV transient wrt ground will couple capacitively into the circuitry quite readily.

Shields can help (or hurt, as the ground coupling example illustrates).

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