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I have a testbench and a verilog modules. I want to write ouput of the testbench to a file anmed as output.txt. While doing this job, I want to use $monitor.

Is it possible ? If yes, can you give me pseudo code of that segment ?

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2 Answers 2

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use $fmonitor:

integer f;
initial begin
  f = $fopen("output.txt");
  $fmonitor(f, "time=%5d, v=%h\n", $time, vv);
  #1000 
  $fclose(f);
  $finish;
end
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I have wrote Makefile to meet that desire ;

default :
iverilog -o verilog_testbench lab_work.v test_bench.v 
odt  :
./verilog_testbench > simulation.odt
txt  :
./verilog_testbench > simulation.txt

I have tried Taniwha 's answer before, but It did not work. So, I have wrote Makefile.

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