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In some circuits such as crystal oscillators, there is a CMOS inverter with a feedback resistor, they all simply say the resistor bias the 'amplifier' and force it to operate in the linear region, such as Fairchild: CMOS Linear Applications:

Due to the symmetry of the P- and N-channel transistors, negative feedback around the complementary pair will cause the pair to self bias itself to approximately 1/2 of the supply voltage.

But what's the internal working details?

  1. Why the bias point is '1/2' supply voltage?
  2. It seems the '1/2' bias point only work when the input is open, or the source is capacitive coupled with the inverter, right?

The inverter's VTC from Sedra & Smith's book

enter image description here

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Diverger - I recommend to study the V(in)-V(out) transfer characteristic to be found in the relevant CMOS data sheets. As you will see - the output voltage will be at Vdd/2 in case the input also is Vdd/2. Because the transfer curve of the inverter has a negative slope (rising input causes falling output) you can find a stable operating point at V(in)=V(out). This can be simply accomplished using a large feedback resistor Rf between output and input (Rf should be "large" with respect to the overall input resistance of the circuit).

If you are going to use the CMOS device as an analog amplifier you need an input coupling capacitor to separate dc and ac. The gain is relatively large - however, determined by the slope of the transfer curve which has large tolerances and uncertainties. Thus, it is recommended to use signal feedback using a series resistor between signal source and the input capacitor. This reduces the gain, but stabilizes the gain value against CMOS tolerances.

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  • \$\begingroup\$ You are right, if we assume a perfect unity feedback, and from the inverter's VTC, the only point with same input-output value is the mid-supply point. \$\endgroup\$ – diverger Sep 23 '14 at 9:23
  • \$\begingroup\$ Yes - unity dc feedback is ensured for capacitve input coupling. \$\endgroup\$ – LvW Sep 23 '14 at 9:53
  • \$\begingroup\$ Can you explain why use 'large' Rf? \$\endgroup\$ – diverger Sep 23 '14 at 9:54
  • \$\begingroup\$ Consider the overall input resistance, which should be "as large as possible" for a voltage amplifier (similar to the classical opamp inverter topology). \$\endgroup\$ – LvW Sep 23 '14 at 12:54
  • \$\begingroup\$ @diverger you state above "the only point with same input-output value is the mid-supply point" this only true if the transistors are matched (i.e. have the same Ids,on) if one transistor is a little bit less \$g_m\$ then the bias point will swing towards that transistor. The output must also be AC coupled because of this. \$\endgroup\$ – placeholder Sep 23 '14 at 13:20
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With the output of a CMOS inverting gate connected to its input through a resistor, a rising output voltage driving the input past a certain point of equilibrium will cause the output to servo its voltage down until the input gets to that happy point. Conversely, if the output voltage falls below that point it'll be servoed up until the input rises to the happy point and, eventually, a position of "unstable equilibrium" will be achieved where a small external signal applied to the input can effect a large change in the output voltage.

That happy point is arranged to be at about Vcc/2, and this reference goes into the gory details.

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An inverter is just a rather nonlinear amplifier. It is possible to use 'digital' inverters to build some simple analog circuits. Generally, the initial oscillation of a crystal oscillator will be very small, much too small to get to the logic-level threshold of the open-loop amplifier. So adding some feedback allows the small signal to be amplified and fed back around until it has built up large enough. Using a CMOS inverter means that no additional analog circuitry is required.

As for why the voltage is 1/2 of the rails, that involves looking at how the inverter is built. The simplest CMOS inverter is a single NMOS transistor and a single PMOS transistor, connected with the NMOS source on the ground rail, the PMOS source on the power rail, the gates tied to the input, and the drains tied to the output.

CMOS inverter

When the input is low, the NMOS will be off and the PMOS will be on, pulling the output towards the Vdd rail. When the output is high the PMOS will be off and the NMOS will be on, pulling the output towards ground. If the input and output are connected together, the circuit will attempt to settle somewhere in between. It turns out that for most CMOS chips, the transistors are built so that they are symmetrical in terms of their threshold voltages and drive strengths, so the most stable point is just about at Vcc/2. If one transistor had a higher threshold voltage or a lower drive strength, then the output would settle closer to the other transistor. The CMOS devices are designed (and the production process tuned) to make sure this is the case so that logic gates have symmetrical (or as much as possible) rise and fall times. In fact, in an inverter, the PMOS needs to be physically larger than the NMOS in order to get the same drive strength due to the physics of how the transistors work.

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  • \$\begingroup\$ Yes, can you explain how the feedback bias it to 1/2 supply voltage? \$\endgroup\$ – diverger Sep 23 '14 at 5:56
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Consider a simple CMOS inverter composed of one n-channel MOSFET and one p-channel MOSFET:

enter image description here

With feedback IN and OUT are connected through a resistor. Suppose IN is at about 0V. The p-channel MOSFET is on and the n-channel MOSFET is off, so the voltage at OUT is high (at \$V_{DD}\$). Due to the feedback resistor current flows from OUT to IN and charges up the MOSFET gates. This causes the voltage at IN to rise, which turns on the n-channel FET. Now both FETs are on -- the n-channel FET tries to drive OUT low and the p-channel FET tries to drive OUT high. Assuming the two FETs have similar characteristics (which they are designed to in a CMOS inverter) they will balance each other out and both IN and OUT will settle to approximately \$V_{DD}/2\$.

The same argument applies if the voltage at IN drifts too close to \$V_{DD}\$. In that case, the n-channel MOSFET is on and the p-channel MOSFET is off, so OUT is low. Charge is pulled away from the MOSFET gates through the feedback resistor due to the voltage difference between IN and OUT, which drives the voltage at IN lower. This turns on the p-channel MOSFET, which tries to drive OUT high.

In short, the feedback resistor will drive the IN voltage away from the \$V_{DD}\$ and ground rails so the IN voltage will settle at about \$V_{DD}/2\$.

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  • \$\begingroup\$ Not true. If both outputs are OFF, then there'll be no drive for the gate and it'll be left floating. \$\endgroup\$ – EM Fields Sep 23 '14 at 9:19
  • \$\begingroup\$ You mean with floating input, the circuit won't stable itself to VDD/2? \$\endgroup\$ – diverger Sep 23 '14 at 9:48
  • \$\begingroup\$ Given that Vth is ~ 0.5 V and ~ -0.5 V (NMOS and PMOS) and say eh rail is 3.3 V, BOTH transistors will be on. So you have have it exactly backwards! \$\endgroup\$ – placeholder Sep 23 '14 at 10:41
  • \$\begingroup\$ @EMFields: I think Null mean neither MOSFET is 'fully' on, they all work in the 'saturated region'. \$\endgroup\$ – diverger Sep 23 '14 at 14:01
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    \$\begingroup\$ @placeholder: Thank you, but I choose to disengage; there's nothing to be gained by continuing this folderol. \$\endgroup\$ – EM Fields Sep 23 '14 at 19:22
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If you connect the input and output of a CMOS inverter, both the PMOS and NMOS FETs will be drawing current, and the exact voltage it stabilizes at is determined by the relative "strengths" (or current gains, really) of the FETs. It's not necessarily half-supply, but typically it's close. The output voltage stabilizes at the point where the current through both transistors is equal. It's an inverting circuit, so it forms a negative feedback loop when connected this way.

If they have equal strength, then at VDD/2 on the gates and drains the PMOS is sourcing exactly has much current as the NMOS is sinking.

If the PMOS is stronger than the NMOS, then the NMOS will need a little higher gate to source voltage to source a little more current, and the PMOS will need less gate to source voltage, so the bias point shifts higher toward the supply.

If the NMOS is stronger, then the bias point shifts lower toward ground.

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