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When working with single-supply op amps biased to mid-supply ( virtual ground rail ) how does one achieve proper bypassing at the IC given that the virtual ground should be as noise-free and stable as possible?

In the schematic below, lets refer to the amp labeled "IC5B":

enter image description here

Power rail is 5V, labeled as +5V/1, and comes from an LDO. The GND of the LD0 is labeled as ISO_GND. VGND is supplied by a 2.5V, +/-10mA reference IC, powered from the same VDD. The ADA4528 is a chopper amp with a chopping frequency of ~200kHz. The amp's VDD pin is connected to +5V/1 and the amp's VSS pin connected to ISO_GND.

If this were an op amp with dual supplies and didn't care about ground noise, I would bypass each power pin from its respective rail to VGND, like this:

enter image description here

Since the system's entire reference is the VGND plane, and chopper amps draw current in pulses at the chopping frequency, and the op amp's noninverting input pin is connected to VGND and supposed to be noise-free, I am worried about injected noise voltage because of shunted high frequency current into VGND. In that case, would I use only a single bypass cap between the amp's VDD/VSS pins ... like this?

enter image description here

Are there any other considerations from a noise perspective that I should follow in this system?

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    \$\begingroup\$ This is outside my area of real expertise. Also, I am confused about the power connection on the chopper amps. Is the VSS power pin on the chopper amps conected to V- or the midrail reference (VGND)? Either way, what you need to do is bypass the chopper amps from their VDD to VSS. Also, any place on the board where you put caps from V+ to VGND, you should also have a matching cap from VGND to V- (and vice verse). This will create a capacitive voltage divider which will help keep VGND dynamically centered between V+ and V-. Also minimize current on VGND. \$\endgroup\$ – mkeith Nov 6 '14 at 18:52
  • \$\begingroup\$ @mkeith: All power connections are as follows: VDD power pins go to V+ rail which is 5V; VSS power pins go to ISO_GND which is the same as the GND pin of the LDO. VGND connects to pin 2 (the noninverting input) in both pictures in order to bias the amp to mid-rail. By the way, all signals into and out of the amps are referenced to the VGND plane, and thus have a 2.5V offset. I've edited some wording in the original post to make this more clear. \$\endgroup\$ – smoothVTer Nov 6 '14 at 20:01
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I went to a break out session titled "Top 10 Op Amp Mistakes" at a conference not long ago, given by an Analog Devices FAE and this scenario came up. The first option with bypass caps from both power and the ground plane to the virtual ground will be better. Ideally, you'll want to have several caps each, say 10uF, 1uF, 0.1uF, even better, in progressively smaller packages. Of a 0603 and 0402 cap of the same value, the 0402 cap will have the higher SRF. The idea is to extend the SRF of the total capacitance out significantly further than any signal of interest.

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  • \$\begingroup\$ I think the bypass for the chopper amp will be most effective if it goes from VDD to VSS directly. However, in order to maintain VGND as a good reference plane, there needs to be plenty of bypass from VGND to both power rails. This bypass needs to be as symmetric as possible, and caps to the two rails should be placed near each other. Anyway, that is how I see it. ;-) \$\endgroup\$ – mkeith Nov 7 '14 at 1:26

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