# CMOS gate logic switching time based on input vectors

My question is regarding CMOS logic gates switching time based on input.

Say I have a NAND gate and my input vectors are:

00 | 1
01 | 1
11 | 0
10 | 1


So, the output is not switching in case of the first 2 vectors and switches for the rest.

I would like to know if the gate will temporarily lose its Logic 1 state and in the process adding to compute time when the input toggles from:

00 ---> 01


I need to know this as I have built a gate level netlist (verilog) simulator which adds to compute time only when the output toggles. I need to know if my approach should look at the input values instead.

@sanjay: A standard CMOS NAND gate has two PMOS devices in parallel to pull the output (to supply) and two series NAND gates to pull the output down (to ground). If either input is zero, then at least one PMOS is on pulling the output up and at least one of the series NMOS FETs is off preventing the output from pulling down.

So the output will not "lose its state." There can be small glitches seen in the output voltage when the one input changes from 0 to 1 due to gate overlap capacitance in the FETs, but any glitches like this should be small enough that they do not cause the next gate or stage to see a change in the NAND output.

Note we don't usually consider a combinational logic gate as having a "state." In digital design, a "state" implies some sort of memory or latched condition as in a flip-flop or latch.

• Let me rephrase, say an inverter is following the NAND gate. Let's assume a NAND_X4 gate (most powerful driver) and both inputs of the NAND gate coming from Primary Inputs...in this case, will the 00 -> 01 toggle cause inverter output to change temporarily? – sanjay Sep 25 '14 at 1:19
• Since CMOS logic reduces glitches by stabilizing logic value, does this change in input cause the gate to go into a floating output zone? – sanjay Sep 25 '14 at 1:22
• @sanjay Generally, no the NAND output won't change over this transition on one input pin (00->01), and the following (inverter) stage won't see a change at its input. The output of the NAND is 1 whenever either input is 0. As long as the NAND does not have huge gate overlap capacitance and weak devices in it you will not see much or any glitch at the NAND output from 00->01 at the input. – mixed_signal Sep 26 '14 at 1:24
• I agree with you...after some thinking, I also feel that if I actually look at modelling charge sharing and iv characteristics of gates, then I would be looking at a tool like hspice. That would be overkill for a timing simulator trying to perform dynamic timing analysis...in other words, I don't need to consider the glitches – sanjay Sep 27 '14 at 1:38

Logic gates like AND, OR, NOT, and so on are not discretised in time, they don't handle time in steps. At every moment they reflect the input at some earlier moment (a few nanoseconds ago, usually). For various reasons signals can get delayed for a tiny moment of time (line length, capacitance, etc), and as a result for similarly tiny lengths of time your output could reflect a state where one input has changed and another not (yet). These are known as hazards.

If hazards will be a problem on your output, you need to design around them. For counting, for example, consider using Gray code which cycles through all values while only ever changing one bit at a time (but is a bit of a pain to generate in hardware, software has no problems).

Alternatively, start using clocks and flip-flops and allow settle time. Don't be overly cautious. Often, very large systems of gates (eg a whole ALU) can be activated simultaneously and all kinds of hazards generated. As long as enough time is allowed for the value to settle before latching into a flip-flop, then it's not a problem.

The problem is similar to bounce in switches and races in software. Always remove hazards from outputs driving power devices: it's an easy way to screw whatever is connected to the output. Either latch the output with a clocked flip-flop, or use a capacitor, to remove hazards in this case.

• Data hazards might be generated but I'm not concerned about that as I am dealing only with the combinational logic between two flops. To elaborate, I have designed a simulator that adds gate delay to the overall delay only when the output of the gate switches. I am looking to see if I should add some delay in case the output does not switch even when the input switches... – sanjay Sep 25 '14 at 1:59