2
\$\begingroup\$

I am laying out PCB for a stopwatch project that I made couple of months ago. I seem to have taken care of the only sensitive part i.e. crystal, since it is time measuring device. But I also see that in other projects, where we have 16x2 character LCD, that when I connect CPU there's few mVpp of noise at pins 15-16 of LCD(These are the pin for LED backlight) since I don't think this noise is due to LED backlight where is it coming from. I measured it using ground spring between pin 15-16. I was told that since that part is drawing high current (20-30 mA) the transient in other part of circuit is reflected "more" here.

Is this true.?

I checked the power line at other points and I didn't see as much noise as I see at pin 15.

This is the layout I am doing, still not complete.

enter image description here

U3 is my CPU. LCD Will be connected at J6,j7,j8. J9 is the point where I will connect A boost converter(External PCB). So Is my Crystal n caps layout correct, and How should I power my LCD, should the trace be very small, if yes then how much(any math), should I share power line between CPU and LCD or should I use star connection for power as well.

Also regarding the Decoupling caps on vdd of IC. Vdd pin is pin 20 and gnd is pin 10, they are as far away as it could be. Should I connect second pin of cap to pin 10 or to the power supply ground since it's closer to it.

Edit: Added Semi-Completed Layout

enter image description here

Thanks for your suggestions everyone. Above is top view of my semi-complete layout. Trace width for pwr and gnd is 40 mil , and logic is 12 mil and for my 20 Hz pulse output it is 25 mil. Below is it's bottom view: enter image description here

I wanted to ask one more thing regarding Decoupling caps: I have read in a datasheet of an OPamp to connect 0.1uF and 1uF to IC's Vcc. Along the same lines I have connected like 0.1uF and two 1uF to the LCD's Backlight pin, Is it worth doing it or a single 2.1 uF will do the job similar to them. The whole idea for distributing Caps as 0.1 and 1uF is to have smaller cap handle fast transients and 1uF to provide bulk charge. Am I going correct. Also if you see for IC U4 I have connected Decoupling to gnd through a via, and kept via as close to cap as possible, is it enough or is it going to haunt me after production.?

Thank you very much.

\$\endgroup\$
  • \$\begingroup\$ Is the brown/rusty-red area around the crystal on a different layer? It is a helpful to place all the parts, and assume all the tracks will be ripped up, and re-routed several times. So rather than get the tracks around the crystal 'perfect' put all the parts on, with reasonable clearance first. Then try to route, move parts, and rip up tracks until routing becomes easier. \$\endgroup\$ – gbulmer Sep 25 '14 at 12:03
  • \$\begingroup\$ Also, what track/space are you routing to? Some of those tracks look quite thin (though I've been doing a lot of 0.5mm pitch, so my eyes might be misjudging things). \$\endgroup\$ – gbulmer Sep 25 '14 at 12:11
  • \$\begingroup\$ @gbulmer Track width is 12 mil for logic and 40 mil for power and gnd. as for space I haven't put any specific rule, just visually ok separation. \$\endgroup\$ – Sajid Sep 27 '14 at 7:58
2
\$\begingroup\$

In power-plane-layer-less designs you should prefer the power for higher-power devices to route separately from the power to lower-power devices and take care of return-paths as much as possible. That means, if you have cause for worry, route the LED power and its return ground along the same path to avoid interference.

I have to agree with Laszlo though, that in a digital-domain only schematic a few millivolts are not going to give you much grief.

But if you still want to improve the noise immunity you may want to place an extra 10uF or 22uF or something in that range depending on the amount of "ick" your supply might introduce at a load next to the pins that power the LCD, just to take the edge off.

Further you should connect the decoupling capacitances (82nF ~ 330nF, depending on your own transient current requirements) as directly to the pins of your digital devices as possible.

If you then still have worries, a few uH in the path to the uC along with an extra 10uF ceramic will help a lot, but beware that this has serious implications if the uC starts switching things with several mA transient going out of its I/O pins. You stand the risk of effectively increasing what you notice of your own on/off outputs, so you should save this to the very last if you have proven in a test set-up to be bothered by incoming noise more than you expect to cause yourself. (Or have been able to simulate/calculate the effects and weighed them or can use those results to adjust the component values for correct poles/zeroes, etc.)

As for your Crystal Layout, it seems okay to me. I wouldn't be too worried about rip-up and retry, as the ring can function as a reminder to allow for isolation. One thing you might want to think of if you want exceptionally high accuracy is that the uC's pins and your PCB introduce a certain amount of capacitance (between 0.1pF and 4pF are known values) and that you want your PCB tool to make a prediction, or that you might want to measure those, to adjust the capacitors, as the crystal's accuracy is measured at exactly the right capacitance.


EDIT to answer your later questions:


You are correct in your assumption that the differentiation between the large and small capacitors is due to transient speed. Usually you prefer small caps, for size considerations, so a 1uF 0805 capacitor would have a higher ESR than a 100nF 0805 type, but a 1uF with similar ESR as the 100nF type would be at least two to three times as large as the two capacitors together. Not to mention that standard 0805 caps are much cheaper.

As far as the display goes, probably a single 1uF or 220nF 1206 type or similar size should give you the limit of usefulness. Flooding the design with capacitors is not necessary. Also consider that if the display is made properly that all of its chips will have decoupling as well.

The capacitor close to U4: I am assuming your write-protect trace from U4 to the pin header can be a little longer than it is now, as the jumper will be purely DC during operation. So just route that wire on the outside and lay the capacitor directly between the VCC and GND traces, no fiddly business with Via's needed and a better return path for your U4.

Probably it would not make that much of a difference for the levels of "speed" you are thinking about, but as a general design rule every few mm of trace you shorten between the chip and decoupling is going to increase high-speed performance of your digital components and transient/swing performance of your op-amps.

\$\endgroup\$
  • \$\begingroup\$ @AsmyIdof Thank you. Separate Power line. Done Extra Caps. Done Inductor is a no no. As for crystal I Don't need absolute accuracy since the device will be calibrated for time parameter. However I need minimum drift to maintain the calibrated accuracy. Btw would you mind throwing in your suggestion to my last question regarding caps. \$\endgroup\$ – Sajid Sep 27 '14 at 7:53
  • \$\begingroup\$ @Sajid - I added an edit addressing your questions. \$\endgroup\$ – Asmyldof Sep 28 '14 at 0:08
4
\$\begingroup\$

A few mVolts for an MCU is nothing. Even 100mV is nothing in such a circuit, unless you want to use it to measure small signals precisely. However, I cannot see the mandatory 100nF ceramic capacitor as close to the Vdd-GND pins of your MCU, as possible. That capacitor makes a difference!

If you are concerned about the noise related to the LCD backlight, then avoid PWM brightness control of the backlight. Use a series resistor or a pot to set a fixed brightness.

\$\endgroup\$
  • \$\begingroup\$ Yea I'll put them, I have not completed the layout. There's no PWM control. \$\endgroup\$ – Sajid Sep 25 '14 at 9:04

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.