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I have a question on the body effect of MOS transistor. In particular, how does the body effect in PMOS be eliminated (by connecting bulk to source together) while this similar technique doesn't do the same to NMOS?

The answer to this question is given by:http://www.onmyphd.com/?p=body.effect It is saying that PMOS is fabricated as N-well such that such PMOS are physically seperate from each other (seperate from other well) so that you can connect bulk to source to each one of them individually. On the other hand, NMOS shares a common substrate, so if you were to connect the source and bulk, you will have to do so for all NMOS.

However, I still don't see the reason doing this in NMOS will cause any problems at all.

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It works when the source is at the same potential as the substrate. But not all NMOS transistors will have their sources connected to the substrate. Sometimes they are put in series, where the lowest one is connected to the substrate, and then the drain is shared with the source of the next transistor and so on. It's also possible to use an NMOS in a transmission gate. In this configuration, both of the source and drain are connected to signals and neither can be connected to the substrate.

Also, connecting the PMOS well to the source will significantly increase the capacitance between the source and the substrate, which could be a major factor for speed.

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Perhaps looking at it another way, a traditional bulk CMOS process is built on a P-type wafer. This allows NFETs to be built directly in the substrate without "extra" steps. To get PFETs in the same circuit, they need to add N-type wells to the substrate. Since this well is an added feature, you can place it wherever you want. It forms a diode to the substrate (N-type well to P-type substrate) that is reverse-biased (off) as long as the well voltage is positive. This is one of the simplist ways of making a CMOS process.

The impact is that the higher your NFET source voltage (relative to the substrate), the lower your drain current for a given Vgs. For digital CMOS logic, this is often neglected because an "on" chain will have a small bulk-source voltage. Most digital gates I've seen just use a common N-well for the PFETs for space and performance reasons. In linear circuits, such as a cascode amplifier or differential pair, you will start to see this effect, but it also depends on how sensitive the process is to bulk voltages.

There are ways around this limitation for NFETs. One way is to eliminate the common substrate completely, as is done in Silicon On Insulator (SOI). Another way to do it is to have the NFET inside a well. This can be done in a process where a N-type buried layer (or tub) is added to provide an isolation well. There are probably other ways to attack the problem as well.

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  • \$\begingroup\$ Some corrections to improve your answer. Processes from about 0.5 um and down use Epi-wafers, which have a lightly doped layer 5um or so thick (still P-Type), so there is a distinct P-Well implant for the NMOS - this is done so the doping can be controlled like making a retrograde well. The wells are stall all a the same potential though. A triple well process is another way that can be uses to isolate the PWells for the NMOS, used in some DRAM processes. \$\endgroup\$ Sep 26 '14 at 13:30
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From the original post:

"On the other hand, NMOS shares a common substrate, so if you were to connect the source and bulk, you will have to do so for all NMOS." However, I still don't see the reason doing this in NMOS will cause any problems at all.

The reason this causes problems in a bulk process is that all the NMOS devices' "wells" (or bulk terminals) are ohmically connected, not junction isolated. That is, the p-substrate and p-well implants are all the same type and they are all effectively shorted together by a 'resistor network' consisting of the entire p-substrate and p-wells. If you try to bias a substrate contact for one NMOS above ground, then you'll find that you have current flow from that substrate contact to the substrate. (Beware that most simulation systems do NOT account for substrate contact resistance, and you have to make some calculations to determine the current. However, on the layout side there are extraction or LVS stamp rule warnings about such connections.)

PMOS devices, on the other hand, sit in n-wells that are junction isolated from the p-substrate and from each other. That is, there is a reverse biased n-p junction from each nwell to the substrate, so there is no current flow.

The comment by placeholder above mentions triple-well processes. In these, we can build an "isolated pwell" inside a larger (deep) nwell, and then we can have the pwells at different potentials.

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