Using CMOS inverter with crystal and cpacitors, we can make a oscillator. And i find many docs mention the method 'negative resistance'. But, they are not all the same.

The method from TI's doc: Use of the CMOS Unbuffered Inverter in Oscillator Circuits, it separate the circuit as below:

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The method from ST's doc: Oscillator design guide for ST microcontrollers, it separate the circuit as below:

enter image description here

Beside the differences above, there are some other differences:

  1. TI's method use the voltage gain of the inverter, ST's method use the \$g_{m}\$ of the inverter.
  2. TI's method has some limitations on \$R_{f}\$'s value, but in ST's doc, it only say \$R_{f}\$ is used to bias the inverter, but it seems it has no clear 'limitation' on \$R_{f}\$'s value.

I'm a bit confused, what's the 'source' of the differences?


Diverger - I think some confusion can arise because there are always two different ways to explain the functioning of oscillator circuits (models). Normally, we discriminate between two-pole and four-pole oscillators - however, it is important to know that this is nothing else than a different way to describe the oscillation principle.

a) Two-pole oscillators can be described using the concept of negative resistances, and

b) Four-pole oscillators are described using the classical feedback loop (in conjunction with Barkhausen`s criterion).

For most oscillator topologies it is not a problem to explain the working principle using both models (after suitable redrawing and/or change of the common ground). As mentioned in both application notes, the basis for the shown oscillator is the Pierce topology, which very often is considered as a two-pole type (but not necessarily).

  • Regarding your question "gain vs. transconductance": The CMOS inverter has a relatively large output resistance so that it makes sense to use the corresponding transconductance gm for gain calculation. In this respect, of course the connected load is important (in both notes there is an external resistor Rext, which is NOT shown in your drawings!). Thus: voltage gain=gm*load resistance.

  • Regarding the role of Rf: This resistor is necessary to fix the wanted DC operational point (bias point) of the analog CMOS amplifier. In addition, this resistor attenuates the resonant loop and, thus, influences the total loop gain. For this reason there is a recommended/preferred range of values which ensures safe start of oscillations - and this range somewhat depends on the oscillation frequency because the total resistance of the crystal feedback loop depends on frequencies.

  • \$\begingroup\$ 1). Yes, i omit the Rext in my circuit, because according to ST's doc, Rext is not necessary in some cases, such as low amplifier gain. 2). I want to conform which method TI use. A or B? It seems TI doesn't use the 'negative resistance' method, right? 3). Yes voltage gain = gm * Ro||RL, so it dependents on load impedance external. But in TI's doc, "For a CMOS inverter with an open-loop gain, a = 100, the value of the feedback resistor is calculated as ...". how can TI know it's voltage gain before knowing the value of the external component value. \$\endgroup\$ – diverger Sep 26 '14 at 12:55
  • \$\begingroup\$ A or B ? What do you mean? Both diagrams are identical. And yes - they don`t use the neg. resistance model. Moreover, if TI assumes a certain gain a (voltage gain) they have assumed a certain product gm*R=a, why not? \$\endgroup\$ – LvW Sep 26 '14 at 13:04
  • \$\begingroup\$ You've pointed that are two method, A/B means the method you've pointed. voltage gain = gm * ro||RL, the component outside the inverter's output will affect the gain, right? \$\endgroup\$ – diverger Sep 26 '14 at 13:24
  • \$\begingroup\$ Ahh - OK. You were referring to my points a) and b). Yes, I think they are using method b). And - also yes- of course the total impedance connected to the inverter output determines the gain. This impedance, in fact, is a third-order lowpass with additional damping, which produces -180deg phase shift at the wanted frequency. \$\endgroup\$ – LvW Sep 26 '14 at 14:52
  • \$\begingroup\$ Then, TI's doc says "For a CMOS inverter with an open-loop gain, a = 100, the value of the feedback resistor is calculated as ...", how he get the value 100, does it considered the loading effect of the components outside the inverter? \$\endgroup\$ – diverger Sep 26 '14 at 15:41

Regarding the split in the diagrams, ST has separated the crystal equivalent circuit from the load capacitors with which it resonates, whereas TI have chosen to keep all the resonant components together for their description. As LvW points out, the circuit needs a resistance in the gate output to raise the "amplifier's" output impedance.

Logic gates with the same identifying numbers but from different manufacturers perform the same logic function, and are generally interchangeable in logic applications. However, they may be manufactured by different processes, leading to quite wide differences between characteristics in designed and parasitic resistance, capacitance and inductance. Even parts produced with the same number from the same nominal manufacturer vary over periods of years, both by design and manufacturing process changes. Consequently the optimum resistance Rf needed to bias the gate into a linear amplifier mode isn't easy to predict. A very low value is likely to result in inadequate loop gain, and too high a value will create unacceptable phase shifts within the intended operating frequency range.

Logic gates were designed as fast switches, not linear amplifiers, so their performance in a linear circuit isn't characterised in their typical data, and for oscillators they are not a great choice for stability, reliability and reproducibility. They may variously fail to self-start, oscillate on unwanted crystal vibration modes, or even with no crystal connected. Consequently the value of rigorous analysis of their operation in this role is questionable, since the results apply only to the particular make and batch. However, they are cheap and convenient, and can usually be expected to perform adequately with crystals of frequencies 1-20MHz commonly used in digital applications, using example component values provided in datasheets and application notes. If the application is critical, the circuit should be tested across temperature and supply voltage ranges, and with gates and crystals of varying batches, ages and activity.

There is some further information in "Marvin E. Frerking, Crystal Oscillator Design & Temperature Compensation, Van Nostrand Reinhold 1978", pp 100-103 (long out of print, but available free from the Internet Archive, archive.org), along with detailed analysis of many other crystal oscillator designs.


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