I have an VHDL file (a block) with huge count of the different port that can't combined into the one bus because they have different names. These signals will be further connected to different parts of the circuit. I want to "create sheet symbol from HDL" but Altium add each signal separately (not in harness). I'll try to make sheet symbol manually and add port with the right (predefined) harness type. But in the result Altium doesn't understand that VHDL signals included in harness that placed in the "sheet symbol" (green block). How can I link VHDL signals with the harness?

P.S. All signals in VHDL block named with similar prefix e.g. HARN_SIGN_*


1 Answer 1


It sounds like you have no connectivity between your VHDL design and your manually created sheet symbol.

The issue here sounds like that VHDL doesn't have 'signal harness' 'pins' (ports). While you can have a port that's a composite (record) type, all it's elements are required to have the same mode (in, out, inout). Array type have the same name and mode.

Altium appears not to have a mechanism to associate the underlying VHDL design represented by a sheet symbol you create with a signal harness pin - it doesn't match your VHDL entity declaration.

You could overcome this by using Altium's generated symbol in a sub sheet represented by your new symbol with any nets connected from the VHDL generated symbol to signal harnesses, also allowing a name change from the connected nets.

This represents a 'mapping' from the underlying VHDL model represented by Altium's generated symbol to a new symbol with signal harness pins.

Back in the day when schematic editors had textual representations for their schematics and symbols (or could at least import them) we'd write tools to generate portions of schematics and symbols representing this sort of thing, to save the manual work.


The file formats Altium uses are Microsoft Compound Document File Format, and appear to be readily reverse engineering eligible with access to Altium's tools to make simple files used to correlate size and length accuracy (units). It should be possible to programmatically generate information that's so onerous to enter by hand. It wouldn't be a small task, but appears manageable.

There are lots of potential pitfalls, if I recall correctly The geometry used for schematics and schematic symbols (inherited from Protel) is fixed precision, that infers a maximum symbol size, not to mention sheet drawing outline. You'd likely have to break really large FPGA symbols into sub elements.

I recall in ViewDraw breaking the rules and generating a table format, with pin boxes, short wires with signal names, essentially making really big symbols equivalents of component centric net list views. I doubt if Altium's formats are so forgiving.

You could also look for formats that Altium can import. Cadence's Allegro tools have easy symbol and net list formats, although I'd suspect Altium wold want to import .brd files themselves.

It turns out Altuim imports a myriad of foreign design file formats including the Allegro ASCII brd file format (See Importing and Exporting Design Files ). Somewhere I have the Allegro Training Manuals describing file formats, it used to be common as I said to manipulate design files with other tools.

  • \$\begingroup\$ Thank you for your answer. Ok, as I understood I need to make a "proxy" schematic where I should place all ports that present in VHDL description and then combine its into harness? But As I wrote there are HUGE count of ports (about 8k or even 70k) in VHDL description so it's to hard to place manually in schematic. Is there any way to generate Altium SchDoc file? Another words is Altium SchDoc format is open or better is there parser/writer library exists in common languages C/Python/C#? \$\endgroup\$
    – mblw
    Sep 28, 2014 at 4:27
  • \$\begingroup\$ There's an API which allows you to programmatically do things, with examples in various languages. Poke through here (SCH folder) the look for more documentation. \$\endgroup\$
    – user8352
    Sep 28, 2014 at 7:43

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