I'm learning about setup time and hold time of a FF connected to a bus. But the textbook fails to explain exactly why are those needed in an operation. Isn't a FF always powered on and attentive to bus signal changes? How does turning on the clock signal dozens nanoseconds later after the signal went live on the bus help the FF capture it reliably? Does the FF actually sample a continuous segment of signal on the bus, instead of just one instant?(Or is it a difference between theory and reality). If yes, how does that work in reality?



2 Answers 2


You're forgetting a couple of important facts:

  1. A flip-flop isn't a single atomic gate, but made up of multiple gates.
  2. It takes time for a signal to pass through a gate (or propagate).
  3. There is no such thing as a pure square wave.

Take this diagram of a transparent latch:

enter image description here

Assume each gate requires one "time unit" to propagate the signal.

The D signal arrives at the input to one NAND gate at \$T_0\$. It also arrives at the NOT gate at \$T_0\$. It then leaves the NOT gate and arrives at the second (lower) NAND gate at \$T_1\$. So the shortest time before the CLK signal can have any effect on the input NAND gates will be \$T_1\$ since that is when the D signal has propagated to them. SO then the output of those NAND gates will be propagated as stable at \$T_1\$ for the upper one, and \$T_2\$ for the lower one. Then it's on to the next two NAND gates. Those again add 1 time unit to each of the signals. On top of that, the outputs of those then feed back into each other's inputs, so as they change they propagate a new signal through themselves, each adding another time unit.

Only when the outputs have stopped sorting themselves out will the gate be "stable", and that is when it's in the "hold" state. It could be many time units.

Then of course you have the "square" wave, which is far from square. Each change from low-to-high or high-to-low takes time. Only once a signal passes a certain threshold will it be seen as either high or low. Different factors affect how long those transitions take, including the gate capacitance of the MOSFETs in the logic gate, the actual switching time of the MOSFETs, etc.

So you can see there is a certain amount of time taken for a flip-flop to change from one state to another, and at different points during that time different things happen with the gate.

  • 2
    \$\begingroup\$ Technically that's a circuit of a transparent latch, not a edge-triggered D flip-flop. However, the overal point in answering the OP's question is well made, so +1 anyway. \$\endgroup\$ Sep 27, 2014 at 12:44
  • \$\begingroup\$ Blame Google images for that faux-pas ;) \$\endgroup\$
    – Majenko
    Sep 27, 2014 at 12:50

Timing analysis of a logic system depends on having well bounded delays from the clock pin to the output (Q, Qb) pins of the latches and flops. In order to bound the upper limit on the clock to Q delay time, we also have to bound the setup and hold time for data being stable relative to the clock.

Flip flops and latches are essentially the same as clocked comparators in operation. The data input does "continuously" monitor the incoming signal, but it only tries to make a decision and latch the decision (on data being high or low) when the clock is high (for a rising edge triggered latch or flop) or low (for a falling edge triggered one).

For most types of CMOS latches and flops there is a danger of metastability or indecision, or at least a slow decision, when the data is changing too close to the clock edge. The closer the data change occurs to the clock edge that is causing the latch or flop to "latch" the data, the longer it takes the latch or flop output to resolve and change state.

You can run a SPICE or Spectre simulation of a flip-flop and see this for yourself. Run a steady clock signal (square wave) into the clock pin and send in to the data pin a square wave with a period that is equal to some multiple of the clock period plus a small amount. Over time the data edge will "drift" past the clock edge and eventually will land right on top of the clock edge and then continue drifting past. The output will be seen to change state quickly when the data change is far from the clock edge, but then it will take longer and longer and possibly not resolve when the data change is close to the clock change.


Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.