An interface or computer expansion bus gets faster with every version eg. PCI express 1.0 is 4GB/sm, PCI express 2.0 is 8GB/s, PCI express 3.0 is 16GB/s. I understand that things like microprocessors get faster because newer ones are manufactured in better way, but these buses are all physically the same (at least they look like and are compatible). So how come that every version is 2x times faster if it is physically the same as the old one? Why couldn't it be 16GB/s in the first place?
They are multiples ways to improve the bandwidth of an interface or bus:
Overhead encoding : most of old buses use 8B/10B encoding while newer interfaces or bus versions will use 64B/66B and PCIe 3.0 even use 128B/130B encoding. With 8B/10B you send 20% more data than the useful ones. With 64/66B the overhead ratio is only 3.125%. What does that mean ? In general we talk about useful bandwidth about buses. So for a 1 Gbps bus, if you use 8B/10B, the real bandwidth needed is 1.25 Gbps. But the overhead encoding is dependant of the following evolution.
Moore's Law factor: as time flies, you'll have more computing power in a chip and you'll be able to use more powerful algorithms but which need more computing power. You also will be able to make your chip consume less power or having more powerful transceivers. You will also be able to increase the frequency of your bus.
Transceivers: Even if we talk about digital bus, the signal transmitted still need an analog part. This is done by transceivers. They are very power consuming parts of an IC and with the Moore's law and shrinking, you'll be able to have more powerful transceivers than few years behind. You will also have more evolved equalization and pre-emphasis algorithms that will provide the signal to be sent on a longer distance or the same distance but with a higher frequency)
Modulation: Ethernet standards use different Pulse-amplitude modulation (PAM-5, PAM-16) to be able to send more data on the same 4 four pairs cable.
DDR: Use both clock edges to sample data.
This is just some facts that come to my mind.
Why can't we have a very high bandwidth at the beginning ? Try the Moore's law. I think you may be able to have the best of the best in equalization, encoding, modulation, but you'll need a chip that will be very expensive and very power consuming.
Also, for instance PCI Express 1.0 started in 2003 with a bandwidth of 2 Gbit/s per lane. Ten years later, with PCI Express 4.0 we have almost 16Gbit/s per lane. But did we need 16 Gbit/s bus in 2003 ?
Consumer electronics need affordable solutions for their needs. If you try to sell them a 10 Gbps bus for $15 when they need only 5 Gbps for $10, they won't buy it. But bus maker know that there is a higher bandwidth need as time passes and they prepare the evolution to be cost-effective.
Simply because the bus itself is only half the equation.
As you said, processors improve due to smaller scale processing and higher integration. It is exactly these processors that drive the signals on those buses. If they can handle higher throughput speeds and get better noise immunity, the bus gets faster.
Most of this is a matter of balancing needs against expense.
For example, the original IBM PC had an 8-bit bus running at 4.77 MHz. Why didn't it have a wider, faster bus? Because it had a CPU with an 8-bit bus running at 4.77 MHz. A bus that was wider and/or faster could have been built, but there was nearly no point in doing so, because the CPU couldn't use any more than that anyway. To keep costs reasonable, it didn't have a lot of highly intelligent peripherals either, so even though they knew how to build faster buses, using one would have resulted in substantially higher costs but little or no matching improvement in speed--the system spent little enough time waiting for the bus, that even a bus of infinite bandwidth and zero latency wouldn't have made the entire system a whole lot faster.
The PC/AT followed pretty much the same pattern--the width and clock rate of the expansion bus precisely matched the external bus of the processor (16 bits wide, initially 6 MHz, later increased to 8 MHz).
The PCI bus was initially designed about the same way. At the time, Intel was (mostly) building 486 CPUs, with an external bus that was 32 bits wide, running at 33 MHz. The PCI bus did the same.
Then things sort of languished for a while--although PCI designs (under the PCI-X moniker) were widened to 64 bits, and clock speeds increased to 66, 133, 266 and 533 MHz, these (especially the 266 and 533 MHz varieties) never became very popular. Some of the variants were used in some servers, but even there they never became particularly common.
Some of that was driven by politics, but a lot of it was a simple matter of cost and lack of need--most people just didn't have much need (or even use) for a bus a lot faster than basic 32-bit, 33 MHz PCI at the time. Essentially the only place they really gained much from greater bandwidth was for video cards, for which AGP provided a significant improvement in bandwidth at much lower cost.
PCI Express is really much the same way. Bandwidth has generally been quite a bit greater than anybody had any real use for at the time (even in high-end video cards), so building a more expensive bus to get greater bandwidth didn't make much sense. If anything, it would probably make more sense to ask why they bothered building that much bandwidth to start with and/or why they've expanded bandwidth so aggressively, even though almost nobody really needs or uses the bandwidth that's available.
About the only answers I have for that probably sound at least a little cynical. The first is simple competition: even if it provides little real benefit to the average consumer, Intel probably sees at least some competitive advantage to being able to advertise much larger bandwidth numbers than their AMD--and in pushing AMD to spend money on R&D to at least come close to keeping up.
The second comes down to fab utilization. I don't know for sure, but I'd guess that Intel basically builds CPUs in their newest fabs. When a fab becomes obsolete for that purpose, they (most likely) use it to build less critical parts--especially north and south bridges. Since they have fabs that were cutting edge only a few years ago to use, their transistor budget for bridge parts is pretty large, and they'd probably like to use that budget to produce the best part they can, and justify the highest price they can (which kind of leads us back to the first point).
The other side of the coin is that although this may not provide a massive benefit to the consumer, the actual cost to the consumer is also quite low. You can buy a complete motherboard now for less than (for one example) I once paid for a 10 megabit/second Ethernet card--and the motherboard includes at least one (and often two) Gigabit Ethernet connections, six or eight SATA connections, a dozen or so USB connections, etc. In short, even if they built an otherwise-current motherboard with "only" PCI-E 2.0, it probably wouldn't lead to a significant cost reduction.
Of course, a more capable motherboard also makes a (marginally) better long term investment--even if you don't use it immediately, it's possible that (for example) you might continue using that motherboard a while, and eventually upgrade the graphics card to something enough faster that even if it doesn't use the full available bandwidth, it might still use a little more bandwidth than the previous standard supported.
Looking at it from the other direction for a moment: how does having a larger transistor budget and more capable fab lead to a faster bus? At least two points are immediately obvious. One is pretty simple: when you shrink transistors, the input capacitance of a transistor shrinks too. Although you need (and use) I/O buffers, the reduced capacitance leads more or less directly to being able to use faster signaling (i.e., rise time and fall time are reduced). Second, when you can use more logic, it becomes practical to use more sophisticated signaling schemes. For example, an older scheme might have transmitted 10 bits across the wire for every 8 bits of data you wanted transmitted. A newer one (that requires more sophisticated logic) might instead encode 65 bits of data you want sent as 66 bits going across the wire. The first results in 25% overhead, but the second in only ~3% overhead. Of course, you pay for that increased transmission speed in the form of needing more transistors on each end to do the encoding/decoding.
To summarize: the bus bandwidth in typical consumer devices is driven heavily by cost. The technology to build faster certainly exists, but for most computers, there's just not much point.