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How can I determine a seemingly arbitrary signal applied to an FPGA to be the clock signal? Conditions:
1. There is no other clock signal available (as an input to the FPGA) for sampling this input.
2. Assume, this should be the highest speed clock.
3. The source of this signal can be anything, can be generated elsewhere in the circuit and then applied to the FPGA or can be generated only for this block. (In my opinion, the source does not matter.)

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    \$\begingroup\$ What do you mean by "determine"? Do you just want to route an input to a clock? \$\endgroup\$ – pjc50 Sep 29 '14 at 9:11
  • \$\begingroup\$ No. I want to identify if a signal is the clock, given a signal I know nothing about, not even its frequency. \$\endgroup\$ – Suhasini Sep 29 '14 at 9:30
  • \$\begingroup\$ Do you have another clock applied to the FPGA which is significantly faster than the "clock" that you are trying to find? \$\endgroup\$ – Martin Thompson Sep 29 '14 at 14:59
  • \$\begingroup\$ No, I do not. I want this to be the highest speed clock, the fastest. If there was another, I could have easily sampled this signal. \$\endgroup\$ – Suhasini Sep 30 '14 at 4:32
  • \$\begingroup\$ Please correct me if I am wrong. From all the discussion, I infer that I need to use a scope/logic analyzer to know which signal I need to choose as the clock. And, there is no way to sample the highest speed signal; I need a faster reference signal. pjc50's answer states it, but it took Martin Thompson's question to make me understand that. This discussion answers my question satisfactorily. Thanks everyone for your patience with a newbie! \$\endgroup\$ – Suhasini Sep 30 '14 at 5:18
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This is rather like asking "how do identify which electrical potential is the ground". Both "ground" and "clock" are designations rather than physical properties. You choose a signal and use it as the clock.

Now, there are various properties of signals usually used as clocks which a human using a scope would use to identify a clock. High frequency square wave with 50% duty cycle and no modulation or variation? Looks like a clock. You could automate that check if you had another reference clock to sample the signal with.

But there's no strict requirement for those, provided the edges are clean and minimum pulse widths are met. You could have strange duty cycles or very slow clocks; clocking microcontrollers off 32kHz signals in semi-sleep mode is sometimes done. Not all systems have a minimum clock frequency. Some very old systems had handcranks which could be used to generate clock pulses, allowing the operator to single-step a program for debugging.

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By definition, any signal whose edges are used to trigger other activity is a clock. This can be denoted in HDL by creating a process that is controlled at least in part by a signal's rising or falling edges. In a schematic diagram, this is denoted by connecting the signal to the clock input of one or more edge-triggered flip-flop primitives.

Most FPGAs are optimized for synchronous design techniques and have a limited number of signals (maybe 8 or 16) that can be used as clocks, driven by the fact that special on-chip resources are used to distribute clocks with low skew across the chip. If your design has too many signals used as clocks, the synthesis tools will complain.

What exactly are you trying to do?

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  • \$\begingroup\$ Let us assume I have a few signals, say 4, from a previous stage which I need to take as input to my FPGA. One of them is the clock signal which will drive the FPGA. How can I identify (or get the FPGA to identify) which of the 4 is the clock signal? \$\endgroup\$ – Suhasini Sep 29 '14 at 9:25
  • \$\begingroup\$ If you don't already know which signal is meant to be the clock, there's no way of inferring this, other than by examining the signals with a scope or logic analyzer and making some educated guesses. Can you explain why you find yourself in such a situation? \$\endgroup\$ – Dave Tweed Sep 29 '14 at 9:38
  • \$\begingroup\$ I said 4 signals as an example. If I have only one signal, then how can I know if it is the clock signal, without using a logic analyzer. Is there any way to write an HDL code to determine it? I was curious about how we always begin with the clock but never try to find it/code it (at least I've never done it before). \$\endgroup\$ – Suhasini Sep 29 '14 at 9:51
  • \$\begingroup\$ I'm sorry, but you've completely lost me. A signal is a "clock" only by virtue of how it is used in relation to other signals. An FPGA designer generally knows up front which signal(s) are to be used as clocks, and it isn't necessary to "search" for them. \$\endgroup\$ – Dave Tweed Sep 29 '14 at 10:27

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