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I'm trying to have an area of my PCB with the same geometry on the top and bottom copper layers, but I'm having trouble with the polygon on the top layer. I placed vias on the bottom contacts (which will be soldered to two-lead package), and set the 'orphans' setting on the top polygon that overlap the bottom contacts, but they don't fill when I ratsnest the PCB.

Is there any other setting I'm missing?

enter image description here

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    \$\begingroup\$ You could try to give the polygons a rank \$\endgroup\$
    – ChThy
    Sep 30 '14 at 16:35
  • \$\begingroup\$ @maikel Good shot, but I think he has a cutout polygon there. (Just out of curiosity, what kind of device is that?) \$\endgroup\$
    – Dzarda
    Sep 30 '14 at 17:27
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    \$\begingroup\$ @Dzarda it's a photodiode with a rather unconventional package. The pad geometry is custom though, as I want to cool the device with a Peltier on the opposite side of the board. \$\endgroup\$
    – joaocandre
    Oct 1 '14 at 13:09
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If I remember correctly, I had the same issue once. I figured that the polygon cutout would destroy anything underneath it, regardless what rank it had.


There are basically two ways of solving it:

1. Create the outermost cutout so that it only affects the area you want. The cutout would then have a shape of an almost closed letter C.

2. Don't use a cutout at all. Just stack the inner polygons on top of the pour. Use ranking(*) in the combination with a different signal name to automatically create the isolation around those polygons.

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  • \$\begingroup\$ (*) Does anybody remember in what order those rank numbers have to be? I think the higher the rank of your polygon, the more "authority" it will have (to force lower ranking polygons out of the way) \$\endgroup\$
    – Dzarda
    Sep 30 '14 at 18:10
  • \$\begingroup\$ This did the trick. Indeed the cutout area was the problem. With a higher rank on the center pads and a lower rank on the big ground plane, I got the desired layout. \$\endgroup\$
    – joaocandre
    Oct 1 '14 at 11:17

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