I am trying to select a 160MHz clock oscillator for my FPGA. The least expensive I found was either LVDS or LVPECL type for this frequency. I used a CMOS type before, so the output of the oscillator was GND to VDD. I wanted to ask if I could use LVDS or LVPECL type in the same configuration as CMOS, that is, by connecting OUTN to GND in order to obtain oscillations GND to VDD? Would I still need the 100 Ohm resistor between the terminals? Why?

Also, why are these oscillators so expensive? Are there alternatives?

  • \$\begingroup\$ Here's the digikey offering (search for 160 MHz oscillators.) digikey.com/product-search/… What are your stability requirements? You could do an LC thing. \$\endgroup\$ – George Herold Oct 1 '14 at 16:50
  • \$\begingroup\$ @GeorgeHerold Yeah, that's what I need. What's "LC thing"? \$\endgroup\$ – Nazar Oct 1 '14 at 17:11
  • \$\begingroup\$ By LC, I meant an LC oscillator. (Hartley and Colpitts are the classics.. but all sorts of variations.) You probably don't want one, they are mostly higher power than a x-tal and thus spray more RF around... less stable... \$\endgroup\$ – George Herold Oct 1 '14 at 18:14
  • \$\begingroup\$ I suspect a lot of your problems with pricing are the frequency. Why not use a lower frequency oscillator (10-50MHz) and step up the internal frequency with a PLL? Also, if you do use an oscillator with an LVDS output, why would you not feed it into a differential clock input pair configured for LVDS? \$\endgroup\$ – markt Oct 1 '14 at 23:33
  • \$\begingroup\$ @markt That's true. I never interfaced FPGA before, so I thought to first use the clock known to me, before going for something new. Could I increase the internal frequency by more than 2x? I wanted to make 320 out of 160. Can I get 320 out of 40MHz external? \$\endgroup\$ – Nazar Oct 2 '14 at 13:29

(answering from the comments)

You could use a slower, inexpensive oscillator as your base clock, then use a PLL in the FPGA to generate various internal clocks at higher, lower or equal frequencies for use in your design.

The functionality of the PLL's that are available to your design will depend on the type of FPGA; by way of example (modern) Xilinx parts typically allow both multiplication and division by user-selectable integers between 1 and 32. Multiple stages can be cascaded to get finer frequency adjustment.

Extending this to your requirements, you could use an inexpensive 16MHz oscillator as your base clock and use a PLL to multiply it by 20 to 320MHz for use in your design.

Exactly what your options are will depend on what type of FPGA you're designing for and how tight your clock tolerances are. You need to carefully read through the datasheets of everything that you're considering using.

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  • \$\begingroup\$ Nice. Good to know. I thought one could only double the external clock, but 20x that's cool. I will check it out. \$\endgroup\$ – Nazar Oct 3 '14 at 13:26

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