Anti-wind up scheme in the implementation of PID controller

Question

I want to implement designed PID controller. But I am facing the problem of how to limit the saturation limit in both positive and negative direction? I tried using zener diode, but I would like to know if are there any design procedures to get anti-wind up scheme in the implementation of PID controller using zener/diode combination?

EDIT:

this is the designed pid controller and i am using TL084 op-amps which has +15 volts and -15 volts as their supply. when the error is generated, due to integrator the control signal(Vc) output is going to saturation point of nearly 15 volts. I want Vc to be in the range of (0.85-3.8 volts), so that i can give this to SG3524 PWM IC to generate constant duty ratio PWM pulses. I tried by putting zener diode of 3.3 volt rating, but now Vc is coming upto 3.5 volts(basically saturation limit has come down to 3.5 volts) . The problem is how to limt the Vc to the specified range. Can any one please suggest modifications for proper design of anti-windup working scheme of this. Here VFb=-3 volts and VRef= 3 volts

Answer 1

In a PID controller, the "D" term isn't really "derivative", but is actually the output of a first-order high-pass filter with a finite cutoff frequency [if it weren't, any 1GHz noise on the input would be amplified 1,000,000 times as much as a 1Khz signal]. Likewise the "I" term need not actually compute a "pure" integral [which would be the nearly-infinitely-amplified output of a first-order low-pass filter with an infinitesimal cutoff frequency] but may instead be the output of a first-order low-pass filter whose a cutoff frequency correlates somewhat with the machine's slowest plausible response. The gain of the filter may be set to control the DC behavior if the controller has been commanding a certain output for an arbitrary long time but the system hasn't moved; the cutoff frequency may then be set to control responsiveness when things haven't gotten that far. Unlike integrators, low-pass filters with a finite cutoff frequency have a limit to how far they can "wind up" with a given level of input.

An additional approach to prevent wind-up would be to--rather than low-pass-filtering the P term directly, either integrate the difference between the commanded output and what it would have been without the "P" term, or else low-pass filter the actual commanded output. If the output stimulus is pegged to the point that the "P" term isn't able to have its full effect, the "I" term shouldn't operate on the "P" term, but only on its contribution to the output. Using a low-pass filter with this approach will probably be easier than trying to use an integrator, since the filter can be set so that the loop feedback gain doesn't exceed one. Otherwise, when using an integrator and trying to compute the difference between what the output would be with P and without P, it may be difficult to ensure that the integrator's output doesn't generate positive feedback to its input (which could destabilize the system).

Answer 2

Windup (as opposed to overshoot inhibition) is caused by the integrator continuing to integrate even though the output is saturated.

You can simply detect output saturation ( for example with a comparator) and inhibit integration.

Answer 3

Limiting reset windup can be attacked in a few different ways. One way is to use a velocity algorithm that automatically stops integrating when the output saturates.

Another is to reset the integrator when the output is beyond saturation- which can have the effect of not only preventing windup but also suppressing overshoot which would occur with startup of a normally tuned PID controller that did not have windup.

For a 1970-1980 era approach, put a reed relay with a small series resistor across the integrator capacitor and trigger the reed coil with deviation from the setpoint. If you're not trying to do very long integral time constants (eg. 30-60 minutes), an analog switch may have low enough leakage that it can be used.

Answer 4

A number of ways todo it.

The entire PID (do you really need D?) is operating over +-15V BUT the resulting signal needs to be 0.85 --> 3.8V thus a final gain & offset stage to scale the output to this range would ensure a suitable signal.

This however will not solve your windup issue, especially considering you are driving the OPAMPS into saturation (and once in saturation their response is sluggish)

So... if you were to put 2 10V zeners in a back to back arrangement across the feedback capacitor of the Integrator you would stop the OPAMP saturating.

You could add a final clamping stage as well to help

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