I always imagined the photolithographic microchip manufacturing to be a 2D layer creation process without layering, thus creating a topological problem for circuitry when you have some \$K_{3,3}\$ or \$K_5\$ in it, which would certainly be the case for any non-trivial design.

And there are papers out there talking about producing "3D" chips with multiple layers to save space, thereby adding to the confusion.

Yeah, that's sad, but that is what I learned in school, a bunch of mysterious riddles. It's no wonder people start conspiracy theories about aliens catering those technologies to us.

So how can we build complex processors and chips just using a 2D topology ?

  • \$\begingroup\$ More images of the metal layers. FWIW, we were taught about multiple metal layers, and my major wasn't even in electronics. \$\endgroup\$ Oct 8 '14 at 0:58

It turns out that there are layers, but people sometimes skip those when talking about how a microchip works.

The process that introduces layers is called Back end of line, or BEOL.

It basically works like this:

  • Create the 2D chip layer using photolithography
  • Apply an insulating layer
  • Drill holes into that layer
  • Apply a conducting layer, also filling the created holes and create circuit paths or interconnects
  • Repeat those steps as often as needed and your manufacturing process and maybe other considerations such as thermal design allows
  • \$\begingroup\$ "Or like taking apart a cat to see how it can be alive." :D \$\endgroup\$
    – Doombot
    Oct 3 '14 at 14:23
  • 1
    \$\begingroup\$ Consider removing the snarkyness from your answer. It would be better without the snarkyness. In my degree we definitely covered how chips are fabricated, you're own experience clearly differs. \$\endgroup\$ Oct 4 '14 at 4:26

There have always been at least two conductive layers on chips that can be used to route signals — the silicon itself and at least one metal layer.

In the earliest manufacturing processes that had only one layer of metal, "jumpers" that allow signals to cross could be created either by diffusing or implanting a conductive path into the bulk silicon, or by creating a path in the "poly" (polycrystalline silicon) layer that was used for the MOSFET gates in some processes. Vias (holes) in the insulating silicon oxide layer allowed current to flow between the layers where needed.

Modern chips, especially high-density, high performance logic chips, have many layers of metal and oxide — 6 or 8 or more, similar to a multi-layer PCB.


Here is SEM (Scanning electron micrograp) showing a cross section across the width of a couple of transistors.


Labels on the right hand side is function/position in stack. Labels on Left hand side are materials.

The black vertical structure connecting the gate to the 1st metal layer is called a contact. It is comprised of a Titanium seed layer, A TiN barrier layer and a Tungsten plug.

Interlayer Via's between M!,M2,M3 and M4 are not shown.

As a bonus, there is something very unusual about this structure. can any one say what it is? reply in the comments.

  • \$\begingroup\$ Well, trench isolation may be considered very unusual for some of us. Others, probably not :-P \$\endgroup\$
    – user49628
    Oct 3 '14 at 23:29
  • \$\begingroup\$ Note for anybody looking: this is quite old fabrication technology--probably 10-15 years old or so. Aluminium metal and tungsten plugs haven't been used in most new fabrication for years. In a current process, expect to see copper for both the metal layers and the inter-layer connections. \$\endgroup\$ Oct 4 '14 at 15:35
  • \$\begingroup\$ @JerryCoffin that is correct \$\endgroup\$ Oct 4 '14 at 16:11
  • \$\begingroup\$ @JerryCoffin The transition happened in around the 130 nm node, and varied according to company/process. That being said, there are still quite a few fabs running these processes for MEMs, sensors, Automotive and High Voltage. So it isn't out of date. Just not what is used for SOC's, processors and memory. \$\endgroup\$ Oct 4 '14 at 16:22

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