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I have implemented the following online adder for signed digit using vhdl code and I have simulated my design according to the example table shown in the figure attached the problem is I am not getting the first result which is "10" for Z+ and Z+ and at some point a combination of XX and YY gives different ZZ

I also did not understand the happening operation since if I normally add the given bits I do not obtain the same result

Is there a special conversion happening?!

adder design numeric example

an example of 11111111 - 11111111 to check whether the result is satisfying but I did not get a 0000 0000 result in the simulation, although I got the table result by simulating the same input values in the figure

simulation

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_textio.all;
use IEEE.std_logic_arith.all;
use IEEE.numeric_bit.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_unsigned.all;
use IEEE.math_real.all;
use IEEE.math_complex.all;

entity sD_adder is 
port ( clk,rst : in std_logic;
         x_p,x_m,y_p,y_m : in std_logic;
         z_p,z_m : out std_logic
        );
end sD_adder;

architecture cSadd of sD_adder is
signal sig_xm : std_logic;
signal sig_zp, sig_zm : std_logic;
signal n_sig_xm, n_sig_ym, n_sig_w2m,n_sig_g2p : std_logic;
signal sig_g3, sig_h2, sig_w2m : std_logic;
signal sig_g2p, sig_g2m, sig_w2p : std_logic;
signal sig_z2p,sig_z2m : std_logic;

begin

    n_sig_xm <= not(x_m);

    FA_add1: entity work.add_sig 
    port map( a => x_p,
                 b => n_sig_xm,
                 cin => y_p,
                 sum => sig_g3,
                 cout => sig_h2);

    reg_ff1: entity work.d_ff 
    port map( clk=>clk,
                 rst=>rst,
                 d=>y_m,
                 q=>sig_g2p
                );

    reg_ff2: entity work.d_ff 
    port map( clk=>clk,
                 rst=>rst,
                 d=>sig_g3,
                 q=>sig_g2m
                );  

    n_sig_g2p <= not(sig_g2p);  

    FA_add2: entity work.add_sig 
    port map( a => sig_g2m,
                 b => n_sig_g2p,
                 cin => sig_h2,
                 sum => sig_w2p,
                 cout => sig_w2m);

    n_sig_w2m <= not(sig_w2m);

    reg_ff3: entity work.d_ff 
    port map( clk=>clk,
                 rst=>rst,
                 d=>sig_w2p,
                 q=>sig_z2p
                );

    reg_ff4: entity work.d_ff 
    port map( clk=>clk,
                 rst=>rst,
                 d=>sig_z2p,
                 q=>z_p
                );

    reg_ff5: entity work.d_ff 
    port map( clk=>clk,
                 rst=>rst,
                 d=>n_sig_w2m,
                 q=>z_m
                );
end cSadd;
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1 Answer 1

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Is there a special conversion happening?!

Your image for slide 25 corresponds to figure 9.10 found on Page 506 and slide 27 corresponds to table 9.3 found on Page 507 in the book "Digital Arithmetic" by Miloŝ D. Ercegovac and Tomás Lang, 2004, ISBN: 1-55860-798-6.

If you look in the book the text below figure 9.10 (b) on Page 506, Example 9.2:

The signals in Table 9.3 correspond to Figure 9.10(b) and signed bits are encoded using 9.18.

Note that during cycle 0 the result digit z0 - 1 is produced. Although this might be interpreted as an overflow, the range of the result remains less than 1 since the next digit is -1. See also Exercise 9.10.

9.18 is given on Page 505 -

rule 9.18 applied to Figure 9.10

These are not present on your not shown slide 26.

And under 9.5 Exercises, MSDF Addition/Subtraction, Page 537:

9.10 Consider radix-2 online addition with operands satisfying x + y < 1.

(a) Perform the addition algorithm to show that if z0 = 1, then the next nonzero result digit must have a value -1.
(b) Devise a modification to the online addition algorithm to produce z0 to 0 and develop the corresponding design.

A check of the ERRATA shows nothing affecting these pages under Chapter 9.

You're not demonstrating any VHDL code. Why the tag?

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  • \$\begingroup\$ Sorry I added the top level design. I do not have the book I found these slides online and got them I have tried an example of 11111111 - 11111111 to check whether the result is satisfying but I did not get a 0000 0000 result in the simulation, although I got the table result by simulating the same input values in the figure this is what I am not getting to understand \$\endgroup\$ Commented Oct 5, 2014 at 15:47
  • \$\begingroup\$ Hello Again, i have solved the pending issue of the output it turned out that initially i am not setting the inputs to 0 each and they are assigned the unsigned value. after assigning 0 to each input and inputting 0's for 3 consecutive clock cycles before starting the bit stream I have obtained the correct subtraction result \$\endgroup\$ Commented Oct 8, 2014 at 9:47

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