At RESET, the MMU is usually 'off', i.e. it doesn't do any translation of memory addresses. So the RESET vector is retrieved from BIOS EPROM/Flash because the BIOS memory can actually be at that physical address.
The CPU will eventually switch the MMU on, when enough of the MMU's data has been set up. For example the MMU may have tables, in memory arrays, which will convert a virtual address to a physical address.
There are several types of MMU. The simplest have a base address which is an offset into physical memory, and a limit, which is the largest address that a program can access. This type is common in 32bit MCUs.
More complex MMU's will create the illusion of virtual addressing. A programs address space appears to be contiguous for program and data, but actually isn't, and some of it may be stored on an external storage system like disk or SSD.
The MMU is 'on-chip' in modern CPU's. They were separate off-chip units for some CPU's in the 70's and part of the 80's.
AN MMU has a very 'intimate' relationship with the CPU. Every access to memory goes via the MMU. The MMU can prevent any instruction completing an access to memory. For example a load or store instruction, transferring data between the CPU and memory, might have to be prevented from completing because it is using an address which is not valid. So the MMU needs a fast, synchronised integration with the CPU.
For a CPU capable of virtual addressing, the MMU can prevent an instruction completing for a 'missing' virtual memory page by interrupting the CPU in mid-instruction. That CPU state is stored, and the process to retrieve the missing page from external storage started. Other programs may be run in the meantime. Eventually the page is loaded into memory, the page 'fixed up' in the MMU tables, so that it is valid, and then the incomplete instruction rerun to completion, possibly millions of instructions later.
There is a choice about the relationship between cache memory and the MMU. A cache might be indexed by physical memory addresses, or virtual memory addresses. If the cache is indexed by virtual addresses, lookup in cache may happen in parallel with the MMU. If the cache is indexed by physical addresses, lookup happens after the MMU has translated a virtual address to a physical address.
An MMU could not map video memory into the CPU's address space unless the video card already makes the video memory look like normal memory. The MMU doesn't perform any magic, it does address translation between the CPU and memory access. The MMU is set up for each logical (OS) process, e.g. separate application. The MMU can 'hide' parts of the address space from a process, and normally does. So the MMU could prevent a process accessing video memory if it is part of the CPU's underlying address space.
It is the MMU which allows an OS to create a virtual memory environment for processes. The OS is mostly constrained to use whatever virtual address architecture the MMU provides. The OS and MMU don't have to be exactly aligned, for example OS could use bigger pages than the MMU supports, but it would be extremely awkward for the OS to try to use smaller pages.
It is the MMU which enables the OS to provide the illusion of virtual memory. Without a suitable MMU, it would be impractical to provide virtual memory.
(Without a virtual memory capable MMU, the illusion of virtual memory, containing on process, would be managed by an interpreter like the Java Virtual Machine (JVM), or the .NET runtime. They act upon every instruction to ensure the code of the Java/C# program can't damage anther program being run in the same address space.)
Typically the CPU runs in a couple of different 'modes', and the MMU wil treat an address differently depending on the mode. The OS will run in a more privileged 'mode' than a user process.
An MMU which supports virtual addressing will intercept every user-process access to memory (for both instructions and data) and convert the virtual address to a real, physical address. This translation doesn't necessarily happen. The MMU's translation tables also carry control bits, which the MMU enforces, which allow the user process permission to read, execute, or write to the physical address.