What happens to AVR registers during multi-cycle instructions?

This is more of a theoretical question... (Also my first on Stack Overflow)

I am wondering what happens to Atmel AVR microcontroller (i.e. ATTINY85) registers during a multi-cycle instruction.

i.e. ADIW takes two cycles to add an immediate to a two-byte (word) register.

I imagine that during the first cycle one of the bytes is operated on, and then in the next cycle the other byte is operated on. But is this process defined anywhere I can read? And what about the other multi-cycle instructions?

Essentially I'm interested in the state of the microcontroller after each individual cycle, even within multi-cycle instructions.

• I think that you'd be very hard-pressed to be able to get this information from anyone other than Atmel. At the worst it would be a trade secret, at best it would be completely irrelevant unless you wanted to copy the MCU. Oct 6 '14 at 4:38
• I see. Thanks, Ignacio. I just realized that I could manually externally clock the MCU and then reset it during an instruction. I'm not sure if the registers (SRAM) initialize, but this might be worth a try.
– Tristan
Oct 6 '14 at 11:59
• While interesting to know, unless it effects measurable behavior, you wouldn't even need to duplicate this if you were trying to make a work-alike processor (simulator, fpga soft core, etc). Presumably interrupts cannot insert themselves in between - or if they do, the first operation is uncommitted and ends up being repeated after they ISR. Oct 6 '14 at 14:52
• @ChrisStratton, agreed. It's more of a theoretical question of our curiosity (for a conceptual art book I'm working on that includes a simulation of code running on an MCU). I'm going to try a test where I manually externally clock the MCU and reset it in the middle of a multi-cycle instruction. I believe the machine registers will still be intact, and I can have the MCU output their values. Oct 6 '14 at 16:33
• I just did a hardware test in the studio and can confirm that ADIW updates the lower result register after the first cycle and the upper result register after the second cycle. To do this I manually clocked the MCU externally via another chip's output and reset the original MCU in the middle of the ADIW instruction. On reset, the MCU then tested its lower and higher result registers, and interestingly only the lower result register had been updated. If I instead reset the MCU after the complete ADIW instruction, both the lower and higher result registers were updated. Oct 6 '14 at 22:41

Here is my interpretation:

In order for a 8-bit uC to do 16-bit maths, it has to first calculate the lowest significant bits then moves to the highest significant bits, so first cycle adds 8-bits with a carry then adds that carry to the higher 8-bits.

In abstract sense 8-bit can't do 16-bit calculation in a single instruction as results affect each other.

• This isn't necessarily true. While it'd be an unusual design, it's entirely possible for a microcontroller with an 8-bit memory bus to have a 16-bit adder internally, allowing it to perform this addition in a single clock cycle. It'd still take multiple clock cycles to read/write a 16-bit value, but it could do them in any order it wanted.
– user39382
Sep 7 '16 at 20:14
• I meant 8-bit CPU as well not only memory. You are welcome to correct me if I am wrong, but CPU and memory mismatch is strange for me, do you know any MCU does this? Sep 8 '16 at 4:41
• @duskwuff: Not only possible for a CPU to have an internal ALU wider than the memory bus, but actually implemented and commercially successful -- the Motorola 68008 and the Intel 8088 used in the original IBM PC both have 16-bit ALU and 8-bit data bus, and I'm pretty sure so does the Motorola 6809. Nov 10 '16 at 15:01