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Here is the deal..

I need to transmit data to 8 identical components. Each component has a clock and an input signal.

  1. MCU only sends data. Components only receive data.
  2. All 8 components are the same and receive the same 366 bit stream format (only with different values)
  3. All components use the same clock.
  4. Data should be transmitted at 25Mhz, Clock should also run at 25Mhz.

This is a job for an FPGA but I'm trying to get away with doing it on a 120Mhz MCU. What would be the best way to approach this task? I cant send the data in serial (sending the data to each component at once) and I couldn't find an MCU with 8 SPI units.

All help would be appreciated.

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  • \$\begingroup\$ Do the receiving components have slave select pins? \$\endgroup\$ – Dan Laks Oct 6 '14 at 21:01
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    \$\begingroup\$ Could you somehow misuse an LCD interface or a DMA controller? \$\endgroup\$ – Wouter van Ooijen Oct 6 '14 at 21:02
  • \$\begingroup\$ Are you asking what Fan-out to expect? What are the components that the MCU is transmitting to? \$\endgroup\$ – gbulmer Oct 6 '14 at 21:03
  • \$\begingroup\$ No Slave selection pin. An LCD interface or DMA controller sounds promising! \$\endgroup\$ – Gilad Oct 6 '14 at 21:04
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Well, if your chip has an external memory interface that you aren't using then you might be able to do something a little bit naughty, presuming the external memory interface can be configured properly. The idea is simple: connect all of the MOSI pins on the chips in parallel to the data bus pins with one MOSI pin per data pin, and conect all of the clock pins to the data bus clock, possibly with a buffer. Then all you need to do is configure the external memory interface to run with the correct baud rate, and write the data to the memory mapped region with the DMA engine. Naturally you will need to reformat the data so that bit 0 of each word corresponds to the first peripheral, bit 1 corresponds to the second one, and so on.

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If the receiving components don't have slave select pins, you can use tri-state digital buffers to emulate slave selection. These kinds of buffers have enable pins that can put each buffer circuit into a tri-state (high-impedance) mode if desired. That way you can tie the CLK pin of the MCU to the inputs of each buffer and only enable one at a time. In the circuit below, I've only shown 3 components to keep the circuit conceptually simple. Expanding to 8 should be obvious.

schematic

simulate this circuit – Schematic created using CircuitLab

The pull-down resistors are necessary because the CLK pins are inputs on the component side. When you tri-state a buffer output, it will be seen as a floating pin to the CLK inputs. Therefore, a the pull-down will force the voltage to be a clean low signal when the buffer is tri-stated.

Off the top of my head, I recently used a 74LVC125A, which is a 3.3V quad buffer with tri-state functionality. Using two of them gives you 8 tri-state buffers. There are, of course, several other buffers available.

Here is the logic diagram from a representative datasheet as an example: enter image description here

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    \$\begingroup\$ Eh, you probably want to put the gates on the CLOCK and not the data. Otherwise, you will shift in a bunch garbage. \$\endgroup\$ – alex.forencich Oct 6 '14 at 22:22
  • \$\begingroup\$ I addressed that point in my 2nd paragraph. Although I agree that buffering the CLK signal alone is a cleaner way to do this. I'll update my answer to reflect that. \$\endgroup\$ – Dan Laks Oct 6 '14 at 22:26
  • \$\begingroup\$ If you don't gate the clock and you don't have a CS line, then you will ALWAYS shift in something. You can add pull downs to make it shift in zeros, but you're still shifting in zeros. The correct solution is to connect the MOSI lines in parallel and then supply the clock to one chip at a time. However, you need to make sure that clock signal does not contain any glitches. I would recommend AND or OR gates over tristate buffers for this reason - it will hold the clock high or low when disabled (high for OR, low for AND - think about it). \$\endgroup\$ – alex.forencich Oct 7 '14 at 8:40

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