As an individual also without an EE background, I genuinely understand your frustration that “I found some "quite similar" topics when posting this, but can't understand at all”, because I was on the same boat! You are right in believing that there should be an easier explanation that makes more sense to non-engineer people. If you prefer video to texts, here is a 10-min vid that explains the essence of latches and why they work as memory unit:
The trick lies in moving away from truth-tables through approaching logic gates from their physical component: transistor—electricity controlled switches. Apply high voltage to it, it will become a conductor, apply low voltage to it, it is an insulator. There is the other type of transistor, but for simplicity, we just use the high voltage input --> conductor, low voltage input-->insulator as an example.
There are only two ways to connect two switches: either connect them to each other as NAND, AND gate, or connect them independently to the power line as NOR, OR gate:
What distinguishes NAND from AND, NOR from OR is where to take output: closer to high voltage end or ground, before or after the resistor. For example, NOR gate naturally outputs from closer to high voltage end and below the resistor so when both transistors are off, the output is connected to the high voltage end, displaying a high, or ‘1’ you may say. When EITHER transistor is conducting, output will be connected to the low voltage end, hence displaying a low, or ‘0’:
With these physical connections in mind, it is very easy to proceed WITHOUT truth-tables. The trouble with the latch structure is, two logic gates are feeding into each other, so there are only two externally controllable inputs. Hence if you start from the truth-table, you will end up with a chicken-and-egg problem: to know the input, you have to know the output which comes from the input….
But there are two types of inputs: input that can totally determine the output by itself so that we can ignore what the other input is. For NOR gate, output is determined by EITHER of the two routes, as long as one is conducting, output will be determined. Hence a high voltage is enough to determine the output of a NOR gate:
This allows us a definite direction to approach the latch structure: Whether we have input pair of (1,0) or (0,1), always start from the ‘1’ side, because it will force a definite output. For example, if we have (high, low) or (1,0):
If the (1,0) switches to (0, 1), the above steps simply switch positions.
I left a ‘why’ at step 4, asking why would we want to feed back this way, it will help us store a bit, as we will see later.
If we feed (0,0) or (low, low) to both gates, then there are two possibilities:
Because NOR gate naturally outputs high, since it is connected to high voltage end naturally, both outputs will travel to the other gate’s input side, there is no guarantee they will reach both gates at the same time. Whichever travels faster will shut down the other gate’s output! This is why (0,0) is unstable.
So to use NOR latch as memory device, we have to make sure the unstable case never shows up. The trick is in attaching two control gates to the latch:
This way, whether input is high or low, it can always pass to the output side, so that we can always write data when control is on. The feedback is to get ready for locking down data when we turn control off!
To store the data, we have to cut off input changes from affecting outputs. This is achieved by turning off control:
So either (1,0) or (0,1) will switch to (0,0) case, you will see why (0,0) will lead to unchanged results: Because only one side will see a signal change from high to low, but it does not matter, since it has a backup to sustain the loop!
Because AND gate will output low if one input is low, hence trumping the input. So that however input changes won't affect output now.