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At first, I have to say, I'm not in Electrical Engineering, I'm studying for Computer Fundamental, and this question popped up, after a while considering, I decided to post it here.

I found some "quite similar" topics when posting this, but can't understand at all. Maybe because the OP and the answer providers are talking things like electrical engineers!

I can understand basic logic gates and basic flip-flop

This is the question:

The figure shows an RS flip-flop using two NOR gates. Which of the following is the correct truth table for the flip-flop? Here, “unchanged” shown in the table means the outputs maintain a previous state, and “unstable” means the outputs are in an unstable state.

enter image description here

enter image description here

This is the truth table I found on the internet, which indicates a is the right answer:

enter image description here

What I don't get here, is why Q = 0 and Q = 1 when S=0, R=1 and S=1, R=0 respectively, according to NOR gate truth table Q should be 0 and 0?

enter image description here

And how can we determine that Q will be "no change" or "unstable"? I believe there is a clear explanation for people like me can understand it, not only engineers!

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3 Answers 3

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Reset pin going high causes the output to go to zero.

Set pin going high causes the output to go to one.

This is the function of an SR(Set-Reset)-Flip Flop, which acts as a single bit "memory". They latch their outputs due to the interconnected gates, as you see in the first diagram.

Nothing happens to the output when the inputs are not changed. Bad/strange things happen when both inputs are changed at the same time to a LOW state. Circuits designed with these can have strange effects if careful measures are not taken to avoid race conditions or clock(if clocked SR flip flops)/gate delays causing the simultaneous inputs of 0 into S and R.

The truth table of the NOR gate is important because it shows how the two parts of the SR Flip Flop interact - the NOR gate's outputs are fed into each other's inputs, which gives you the latching effect of the output.

You can put both S and R inputs HIGH at the same time if you wanted, but it does not form for to the digital theory of "Q and NOT Q" outputs, so it's not normally acceptable and is called "illegal" in the truth tables.

Bad things happen with both inputs are set low, if both inputs were previously high, because of the gate delays of the NOR gates.This can cause oscillations of the output due to the feedback in the circuit.

You can read more about these race conditions from here and here

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    \$\begingroup\$ @hoangnnm Q of each NOR gate is attached to the input of the other NOR gate, meaning one's state influences the other one's state. The result of this crossing of inputs/outputs gives you a latching ON output, or a latching OFF output, and only changes state when the S or R pins are set appropriately \$\endgroup\$
    – KyranF
    Commented Oct 7, 2014 at 8:51
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    \$\begingroup\$ @hoangnnm The output of the latch will be undefined at initial conditions. The output of the latch will go high when the S pin is driven high. The output Q will remain high forever, unless changed. The output will go to zero if the R pin is driven high. The output will then remain at zero forever unless changed. It is an undefined logic output (could go either way) if both pins are driven high at the same time. This allows the device to act as a "latch" which when set, stays that way until reset. If the output is already zero, making the R pin go high will do nothing. Same as S pin and output \$\endgroup\$
    – KyranF
    Commented Oct 7, 2014 at 8:58
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    \$\begingroup\$ @hoangnnm each NOR gate has it's own Q value, but when looking at the final SR latch it has an overall Q value (output). Q is merely set or reset, depending how you apply inputs to the device \$\endgroup\$
    – KyranF
    Commented Oct 7, 2014 at 13:27
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    \$\begingroup\$ @KyranF: If both inputs of an OR latch are driven high, both output will go low, and stay low, for as long as both inputs are high, so the outputs are not undefined, they're clearly defined. \$\endgroup\$
    – EM Fields
    Commented Oct 9, 2014 at 23:52
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    \$\begingroup\$ Gate delays, imperfect timing, the fact there are 4 inputs to NOR gates in an SR latch, mean this wont really happen @EMfields \$\endgroup\$
    – KyranF
    Commented Oct 10, 2014 at 4:50
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SOME BACKGROUND...

Looking at the graphic, below, the lower image shows the logic symbol for a conventional positive true NOR gate, and the upper image shows the symbol for its so-called DeMorgan equivalent, a negative true AND.

enter image description here

The truth table shows them to be equivalent, logically, and the easy way - for me - to relate [to] them is to consider the straight line input part of the upper gate to denote "AND", and the curvy line of the lower one to denote "OR".

That way, since the upper gate is an AND and is shown shown with two bubbles as inputs, it reads: "two zeros make a one", and the lower gate, being a NOR, reads: "any one makes a zero".

NOW, INTO THE FRAY:

Here's a NOR latch and its truth table:

enter image description here

and to take a look at the input and output states of a pair of NORs configured as a latch, we have:

enter image description here

Where "A" is the basic latch and where red indicates a logic high and blue indicates a logic low.

Referring to "B" and perusing the NOR's truth table, we find that if R is high (a logic 1) then, regardless of the state of U1-2, Q must be low.

The same is true for U2, with the result being that if R and S are both held high, Q and notQ must remain forced low - and are therefore stable - until either R, or S, or both change state.

If we reconstruct the latch using the DeMorgan equivalent for U1, we'll have "C", and since U1-1 (R) and U2-2 (S) are still held high, U1-3 (Q) and U2-3 (notQ) will both remain low, so nothing's changed logically.

In "D", we now force U1-1 low while leaving U2-2 high, which will drive Q high and SET the latch, and since the inputs of U1 are now both lows, its output will go high and force U2-1 high assuring the latch will stay SET no matter what U2-2 does.

In "E", U2-2 goes low but since U2-1 is high the latch will stay SET. It's important to notice that with "R" and "S" both low and the latch SET, the latch is stable and in one of its quiescent states.

In "F", "R" is driven high, which forces "Q" low, and since "S" is already low, U2-1 going low forces notQ high, RESETing the latch and driving U1-2 high, making the state of "R" unimportant.

In "G", "R" has returned to its quiescent low state (making "R" and "S" both low), the latch is stable in its RESET state, (As it was in its SET state with "R" and "S" both low) and is waiting for "S" to go high - as in "D" - to be SET again.

Two caveats:

1) If the latch is powered up with its inputs not floating but without being expressly initialized, it can come up either SET, or RESET, or with both outputs low or momentarily high, but it'll sort out the unstable state(s) and settle into whatever its inputs dictate.

2) If both inputs are taken high for long enough to drive both outputs low and then both inputs are taken low simultaneously, whether the latch will settle into its SET or RESET state is indeterminate, as shown by the latch's truth table, above.

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  • \$\begingroup\$ Thanks, this is very informative, please give me sometimes to fully understand it, I'll get back to you ASAP! \$\endgroup\$ Commented Oct 9, 2014 at 8:33
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As an individual also without an EE background, I genuinely understand your frustration that “I found some "quite similar" topics when posting this, but can't understand at all”, because I was on the same boat! You are right in believing that there should be an easier explanation that makes more sense to non-engineer people. If you prefer video to texts, here is a 10-min vid that explains the essence of latches and why they work as memory unit: https://youtu.be/JavcdC_msts

The trick lies in moving away from truth-tables through approaching logic gates from their physical component: transistor—electricity controlled switches. Apply high voltage to it, it will become a conductor, apply low voltage to it, it is an insulator. There is the other type of transistor, but for simplicity, we just use the high voltage input --> conductor, low voltage input-->insulator as an example.

There are only two ways to connect two switches: either connect them to each other as NAND, AND gate, or connect them independently to the power line as NOR, OR gate: enter image description here

What distinguishes NAND from AND, NOR from OR is where to take output: closer to high voltage end or ground, before or after the resistor. For example, NOR gate naturally outputs from closer to high voltage end and below the resistor so when both transistors are off, the output is connected to the high voltage end, displaying a high, or ‘1’ you may say. When EITHER transistor is conducting, output will be connected to the low voltage end, hence displaying a low, or ‘0’:

enter image description here

With these physical connections in mind, it is very easy to proceed WITHOUT truth-tables. The trouble with the latch structure is, two logic gates are feeding into each other, so there are only two externally controllable inputs. Hence if you start from the truth-table, you will end up with a chicken-and-egg problem: to know the input, you have to know the output which comes from the input….

But there are two types of inputs: input that can totally determine the output by itself so that we can ignore what the other input is. For NOR gate, output is determined by EITHER of the two routes, as long as one is conducting, output will be determined. Hence a high voltage is enough to determine the output of a NOR gate:

enter image description here

This allows us a definite direction to approach the latch structure: Whether we have input pair of (1,0) or (0,1), always start from the ‘1’ side, because it will force a definite output. For example, if we have (high, low) or (1,0): enter image description here

If the (1,0) switches to (0, 1), the above steps simply switch positions.

I left a ‘why’ at step 4, asking why would we want to feed back this way, it will help us store a bit, as we will see later.

If we feed (0,0) or (low, low) to both gates, then there are two possibilities:

enter image description here

Because NOR gate naturally outputs high, since it is connected to high voltage end naturally, both outputs will travel to the other gate’s input side, there is no guarantee they will reach both gates at the same time. Whichever travels faster will shut down the other gate’s output! This is why (0,0) is unstable. So to use NOR latch as memory device, we have to make sure the unstable case never shows up. The trick is in attaching two control gates to the latch:

enter image description here

This way, whether input is high or low, it can always pass to the output side, so that we can always write data when control is on. The feedback is to get ready for locking down data when we turn control off! To store the data, we have to cut off input changes from affecting outputs. This is achieved by turning off control: enter image description here

So either (1,0) or (0,1) will switch to (0,0) case, you will see why (0,0) will lead to unchanged results: Because only one side will see a signal change from high to low, but it does not matter, since it has a backup to sustain the loop! Because AND gate will output low if one input is low, hence trumping the input. So that however input changes won't affect output now.

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    \$\begingroup\$ Please provide links or citations to the original sources of the graphics you copied into your answer. We need to make sure that the creator receives credit for them. \$\endgroup\$ Commented Jun 14, 2020 at 18:26
  • \$\begingroup\$ Thanks for your comment. I am the original creator I guess no need to cite? \$\endgroup\$
    – Shaw Lee
    Commented Jun 15, 2020 at 15:14
  • \$\begingroup\$ Yes, if you are the creator there is no need to cite but thanks, and well done, for the drawings. \$\endgroup\$ Commented Jun 15, 2020 at 15:47
  • \$\begingroup\$ @ShawLee Thanks a heap , for your answer. it has been 6 years, and I passed the exam without any questions related to this (thanks God). Honestly now I don't even remmeber any of this :( . I hope someone else will find this helpful. And once again, thank you for all the troubles you had to provide this excellent answer. Have a good day! \$\endgroup\$ Commented Jun 17, 2020 at 1:21

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