While implementing a T=0/1 protocol using a smart card reader I had obtained from Parallax, I noticed a behavior when applying power to the card. It seems that once the 3.3v VCC pin is brought high, it has a greatly reduced rise time (on the order of 450us).

The 450us timing was taken with no smart card inserted in the reader, and only VCC and GND connected. An oscilloscope was connected to VCC. VCC was applied and the rise time was recorded.

I believe this to be the result of the decoupling capacitor at least, but I'm not certain how the pull-up resistors on CLK and IO might also be contributing (if at all). The capacitor is a low ESR ceramic cap.

I also tried an isolated circuit with a 1uF, 10uF, and 100uF decoupling caps and was able to simulate extended rise times on VCC moreso with the 100uF cap. That leads me to wonder if there's more at play with the smart card reader circuit, like the pull-ups.

My question: Is the increased rise time the result of the decoupling capacitor and/or the pull-ups. If so, how can I best calculate this time, rather than observing it.

Parallax Smart Card Reader

  • \$\begingroup\$ What is your source of VCC? \$\endgroup\$
    – Dan Laks
    Oct 8, 2014 at 16:24
  • \$\begingroup\$ @DanLaks Originally it was an output pin on a microcontroller. Once the problem was identified, all testing took place with a regulated 3.3v power supply. \$\endgroup\$
    – paul_25
    Oct 8, 2014 at 16:50

1 Answer 1


Rise time is determined by how much current flows into the capacitor. T = CV/I, so time increases when current is reduced. Anything that limits the charging current or bypasses it away from the capacitor will increase the rise time. To calculate the rise time you need to know the internal resistance and current limit of your power supply, and how much current any other circuitry might steal.

In your circuit the pullup resistors should normally be open circuit, but they could be switched to either Gnd or Vcc. If for some reason they were connected to Gnd then they could steal current and increase rise time. However the current they would draw is rather small (0.6mA at 3V), so even if CLK and IO were both pulled low it shouldn't have a significant effect.

A rise time of 450us without card inserted suggests that your power supply is current limited to about 67mA. According to ISO7816 the maximum current a card can draw under normal operating conditions is 200mA. Your power supply should be able to supply at least that much, and the rise time should 150uS or less.

When a card it inserted it will also take some current from Vcc, which will further increase rise time if power supply current is limited. Since the card contains an MCU with complex circuitry, its current draw could vary non-linearly or even "randomly", so you should not rely on it being consistent. Using an output pin on your microcontroller to supply power directly is risky, even if it seems to work.

  • \$\begingroup\$ Very helpful information. Based on your response it seems that the capacitor is playing a role in impacting the rise time of Vcc. I noticed this issue as a result of not giving Vcc and the capacitor enough time prior to activating CLK. This had an adverse effect on card initialization. The cards that I am working with max out at a 25mA current draw, so that should be alright for testing purposes. I have also seen different cards exhibit different behaviors with rise time as you mentioned, resulting in a need to set a fairly wide delay for this reader at least (due to the capacitor). \$\endgroup\$
    – paul_25
    Oct 8, 2014 at 23:22

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.