While implementing a T=0/1 protocol using a smart card reader I had obtained from Parallax, I noticed a behavior when applying power to the card. It seems that once the 3.3v VCC pin is brought high, it has a greatly reduced rise time (on the order of 450us).
The 450us timing was taken with no smart card inserted in the reader, and only VCC and GND connected. An oscilloscope was connected to VCC. VCC was applied and the rise time was recorded.
I believe this to be the result of the decoupling capacitor at least, but I'm not certain how the pull-up resistors on CLK and IO might also be contributing (if at all). The capacitor is a low ESR ceramic cap.
I also tried an isolated circuit with a 1uF, 10uF, and 100uF decoupling caps and was able to simulate extended rise times on VCC moreso with the 100uF cap. That leads me to wonder if there's more at play with the smart card reader circuit, like the pull-ups.
My question: Is the increased rise time the result of the decoupling capacitor and/or the pull-ups. If so, how can I best calculate this time, rather than observing it.