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I'm just trying to layout a PCB with CY7C68013A (100-pin TQFP) on it. It's a sort of experiment, so I'd like to use 2-layer PCB, 4 layer PCBs are just too expensive. This leads to some interesting layout issues (note, that I'm more concerned with signal integrity than EMI).

I decided to use bottom layer as a ground plane, yet I have a really hard time choosing the best way to route the VCC trace. There are a few high-speed signals routed from the left and bottom edges of the chip to the connector on the left side of the board (carrying up to ~30MHz signals). There are 3 VCC/GND pairs on the left side, and 3 more on the bottom of the chip, to make things complex - I need to route VCC away from between those fast signals..

This makes it necessary to either:

a) route parts of these signals on the bottom layer and keep most VCC on top

b) route these signals on top of the board and route some segments of VCC on the bottom layer (but this introduces holes in the bottom layer's ground plane, exactly underneath the signal traces, making the return path's loop bigger)

Any advice? Is it OK to route the VCC underneath the chip on the bottom layer? This would let me leave the ground solid under my fast signals.

How about top layer? (this would require a power track connected to the pin from one side, and decoupling capacitor stub track from the other side - that doesn't sound good to me).

Perhaps I'm overestimating the potential issues, but it's interesting problem on its own - I can imagine many projects choosing 2-layer PCBs to lower the costs.

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  • \$\begingroup\$ "note, that I'm more concerned with signal integrity than EMI" ... Aren't those two pretty closely coupled? \$\endgroup\$ – Kellenjb Apr 19 '11 at 16:17
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That's the Cypress FX2LP USB microcontroller (I recognize it because I use it myself). If you're using the Hi-Speed USB transceiver, then you should really go with a 4-layer board. Without that ground plane right below the top layer, it will be near impossible to get the 90 ohm differential impedance that you want for the USB D+/D- lines.

http://www.cypress.com/?id=4&rID=34128 flat out states that 4 layers is required. It also states that controlled impedance is required, but in my experience you can usually get away without it, so long as you carefully research your fab's typical stack-up and work out the right width, space, and height.

http://www.cypress.com/?docID=25406 also provides more info on calculating the width, space, and height for the D+ and D- lines.

4-layers isn't that much more expensive; Advanced Circuits has a 66 each deal for 4 layer boards that I use quite often for projects that use that very chip, as opposed to the 33 each deal for 2 layers.

In regards to your actual question...use plenty of bypass caps, as close to the pins as possible. If you split the bottom layer to have VCC and GND, don't have a trace cross the split on the top layer. Keep all high-speed signals on the top layer because the via inductance can kill what fragile signal integrity a 2-layer board has.

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  • \$\begingroup\$ Indeed, that's FX2LP uC. I'm fully aware of the official requirement to use 4-layer board, and if that was a commercial project I'd not even think about 2-layers PCB :) \$\endgroup\$ – Code Painters Apr 20 '11 at 9:50
  • \$\begingroup\$ I should be able to get 90 ohm differential impedance on 2-layers board with wide traces (my estimates show that ~2mm spaced ~3mm on 1mm thick FR4 are OK - unless I made some mistake). Sure, it's far from perfect, and traces of this size will need some stubs at both ends, but still I hope it'd be good enough. \$\endgroup\$ – Code Painters Apr 20 '11 at 10:01
  • \$\begingroup\$ Are you perhaps alluding to "AN1168 - High-speed USB PCB Layout Recommendations" (a) (b) ? \$\endgroup\$ – davidcary Aug 5 '13 at 17:32
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If your Vcc is properly decoupled it's as good as ground. (There is no such thing as too much decoupling!) I would have no problem routing it underneath the chip. Make sure you have capacitors on it close to the chip's pins, and keep the Vcc traces as short as possible.

If you get into trouble routing the thing you could use zero ohm chip resistors as jumpers to keep traces as short as possible.

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Here's how I've routed 2 layer boards...

  1. Top layer is to move signals north-south.
  2. Bottom layer is to move signals east-west.
  3. Fill the bottom with a GND plane.
  4. Route any high speed or special traces.
  5. Route a single Vcc power bus along the outside edge of the board on the bottom layer. This violates rule 2, but that's OK.
  6. All Vcc traces come off the power bus and run east-west until it reaches close to the chip. Then use a via to get to the top layer and connect normally.

This usually keeps all the tracks spaced out that you can route everything, even if it means a couple extra vias to hop over other traces.

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gridded ground structure

According to the Texas Instruments "PCB Design Guidelines For Reduced EMI", "A two-layer board can achieve 95% of the effectiveness of a four-layer board by emulating what makes a four-layer board better".

The main trick is to use both the top and the bottom layer of your 2 layer board in a gridded ground structure.

I don't think it makes much difference if you route the fast traces on the top or on the bottom. Either way, you're going to have a horrible slot in the ground plane (on the side opposite those high-speed traces) to get the VCC trace where it needs to go.

In either case, a gridded ground structure helps. Add a bunch of GND traces parallel to in-between the fast traces that "stitch over" or "staple over" slots in the ground plane on the opposite side. For example, GND traces between every 2 traces from connector on left to chip on right would look something like:

(top layer)

O---(Vreg)---o----------| (Vcc)
                        |
O-----------------------| (high-speed data)
    o--------------o    | (a ground stitch trace)
O-----------------------| (high-speed data)
                        |
O-----------------------| (high-speed data)
    o--------------o    | (another ground stitch trace)
O-----------------------| (high-speed data)
                        |
             o----------| (VCC)

and

O     o      o (VCC)
             |
O            |
    o        |     o (ground stitch via)
O            |
             |
O            |
    o        |     o (ground stitch via)
O            |
             |
             o

(-- bottom layer, as seen looking through the top layer)

I've seen a rule of thumb that an extra ground trace for every 2 data traces -- increasing the number of traces by 50%, as shown above -- is often adequate. (An extra ground trace for each data trace -- doubling the number of traces -- would in theory be slightly better). Usually the "ground stitch trace" is completely invisible on the final board, because it is completely drowned by a GND copper pour on the same layer. The only evidence of this design is vias scattered all over the board connecting GND pours on the top layer to GND pours on the bottom layer.

4-layer prices

p.s.: You are totally right about the surprisingly high cost of 4-layer boards from most places. However, have you seen the list of PCB fabs at http://opencircuits.com/PCB_Manufacturers ? A few have relatively low prices for 4-layer boards if you're willing to wait for 6 weeks (!) -- for example, as of 2013, OSH Park says "4 layer order: $10 per square inch for three copies of your design. For example, a 2 square inch board would cost $20 [plus shipping] and you’d get three copies of your board."

gridded ground structure references

"A two-layer board can achieve 95% of the effectiveness of a four-layer board by emulating what makes a four-layer board better". -- Texas Instruments. "PCB Design Guidelines For Reduced EMI".

"The gridded ground structure works almost as well as the ground plane, as far as minimizing loop area is concerned." -- p. 7 Tom Williamson. "Designing Microcontroller Systems for Electrically Noisy Environments". Intel Application Note AP-125. 1993.

"AVR040: EMC Design Considerations" http://www.atmel.com/Images/doc1619.pdf

Ross Carlton, Greg Racino, John Suchyta. "Improving the Transient Immunity Performance of Microcontroller-Based Applications". 2005.

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