I have an FPGA design Quartus that compiles and works correctly for a cyclone IV EP4CE15F17C8 (42% used).
I'm trying to migrate same design to a smaller FPGA EP4CE10F17C8, but when changing FPGA device I get compilation errors related to a PLL Megafunction I have:
Error (176554): Can't place PLL "top_level_d9620:top_level_d9620_comp|pll25MHZ_b:G5|altpll:altpll_component|pll25MHZ_b_altpll:auto_generated|pll1" -- I/O pin clock (port type INCLK of the PLL) is assigned to a location which is not connected to port type INCLK of any PLL on the device
I don't know how to avoid this error. Is there a workaround for this? Even if I remove the PLL, I get many errors like this:
Error (176337): Cell top_laser:top_laser_comp|gene_freq_dpi1:U35|retard_t40 fed by 5 non-global control signals -- only 4 control signals may be non-global