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I've just described an UART transmitter and receiver in VHDL. In simulation everything seems to be fine. In FPGA, the loopback interface works well: I push a button, the transmitter sends data, the receiver receives and display in the 7 segment display.

Regarding communication between laptop and FPGA, I am using a USB<->RS232 cable. Using GtkTerm on linux and tera term on windows I can easily send data to the FPGA. The problem is when I try to send data from FPGA to laptop: just a few bytes arrive in the laptop and many of these bytes are wrong. For instance, I send EE EE EE EE EE EE EE, but I receive only EE CF 14.

I have no idea of what the problem is: if it is software (maybe I've configured something wrong or a driver issue?); if it is hardware (faulty cable?) or if it is code (my VHDL code is wrong).

Any ideas on how to solve the issue?

p.s.: I've tried some few uart transmitters besides mine, they also send just a few bytes. p.s2.: some info: 19200 baud; 8 bits of data, no parity bit, 1 stop bit

if code is needed: https://github.com/hdhzero/hivek-io-modules/blob/master/uart/src/uart_tx.vhd

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  • \$\begingroup\$ What clock are you giving the module? What does your surrounding top-level look like? \$\endgroup\$
    – Zuofu
    Oct 10, 2014 at 2:58
  • \$\begingroup\$ The system clock is 50MHz. The clock feeds a mod counter that generates an enable tick for the transmitter and receiver modules \$\endgroup\$
    – hdhzero
    Oct 10, 2014 at 3:06
  • \$\begingroup\$ All the modules can be found at github.com/hdhzero/hivek-io-modules/tree/master/uart/src. top_uart_controller is the top level where I make the pin assignemnts. Uart_controller.vhd basically create instances of the tx, rx and mod counter \$\endgroup\$
    – hdhzero
    Oct 10, 2014 at 3:08
  • \$\begingroup\$ @hdzero: why do you count 16 ticks in your tx module and 8 in rx? \$\endgroup\$
    – Qiu
    Oct 10, 2014 at 14:53
  • \$\begingroup\$ @Qiu In rx, I wait for the first '0' level, then I switch to the data_bits states. I use 16 ticks to sample data, so the middle of the bit is between seven~eight. I simple take advantage of the fact that the counter will overflow automatically. So when it reaches 7, then I set it to 8 (or I could just let it increment). When I set to 8, the counter goes: 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7, which is just the middle of the following incoming bit \$\endgroup\$
    – hdhzero
    Oct 10, 2014 at 15:19

1 Answer 1

Reset to default
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It was really a faulty cable. I don't know if the problem is the chipset itself or a wire. Anyway, I bought a new cable with a different chipset and everything is ok now!

This is the faulty one

Bus 002 Device 008: ID 1a86:7523 QinHeng Electronics HL-340 USB-Serial adapter

This is the one that worked

Bus 002 Device 006: ID 067b:2303 Prolific Technology, Inc. PL2303 Serial Port
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