# Verilog: sampling data in both posedge and negedge of the clock

I have a serial input stream which has left data in posedge of the clock, and right data in negedge of the clock.

I would like to synchronize and bring them to the posedge of the same clock.

I could do that using another clock with twice of the frequency.

How to synchronize the data using the same clock?

reg r;