I am really puzzled by a FPGA synthesis problem on Xilinx ISE.
Precisely, it took me a long hour to discover why a same RTL design (set of VHDL files) works like a charm on a board using a synthesis script, while a second one does not yield a correct behavior. I have not seen any error messages, nor differentiating warnings.
The difference lays in bitgen options :
- -g binary:Yes
- -g DriveDone:yes -g StartupClk:Cclk
Only the second set of options does works.
Could you give me more insight on these two lines ?