I am really puzzled by a FPGA synthesis problem on Xilinx ISE.

Precisely, it took me a long hour to discover why a same RTL design (set of VHDL files) works like a charm on a board using a synthesis script, while a second one does not yield a correct behavior. I have not seen any error messages, nor differentiating warnings.

The difference lays in bitgen options :

  • -g binary:Yes
  • -g DriveDone:yes -g StartupClk:Cclk

Only the second set of options does works.

Could you give me more insight on these two lines ?


  • \$\begingroup\$ How does the one with incorrect behavior fail? If configuration fails entirely (DONE never goes high), then the StartupClk option is a likely culprit. If it's something else, you might want to provide more detail about what went wrong. \$\endgroup\$ – The Photon Oct 10 '14 at 16:05
  • \$\begingroup\$ Can you please tell what exact error did you face with the second image? \$\endgroup\$ – Avin Oct 10 '14 at 18:19
  • \$\begingroup\$ If you specify the configuration clock as the startup clock, you'll have to provide extra cycles of that clock after the end of the bitstream, to allow the FPGA to finish setting up its internal state. If you (or a default) specify some other clock, it will have to exist. \$\endgroup\$ – Chris Stratton Oct 10 '14 at 18:19
  • \$\begingroup\$ This question approaches the problem backwards. These behaviors are adjustable via options exactly because they affect correctness. If the behavior didn't change, why would the options exist? \$\endgroup\$ – Ben Voigt Sep 18 '15 at 14:44
  • \$\begingroup\$ It is not obvious why correctness should be affected here. Where is that documented ? \$\endgroup\$ – JCLL Sep 18 '15 at 15:49

Xilinx has a good build-in help on synthesis, map, P&R and bitgen options. You can open them by opening syntheses/map/P&R or bitgen properties and then clicking on help. This help gives a short overview on every selectable option, it's values and the commandline name.

There is also UG628 - Command Line User Tools which explains the bitgen options (see page 227 ..)

  • binary:yes -> I think this could be relevant if you are using partial reconfiguration technques
  • DriveDone:yes -> many boards connect a programming done LED to this pin, which is actively driven, rather then pulled up by a resistor - impact uses this pin to read back the programming state for the gui
  • StartupClk:Cclk -> Xilinx FPGAs have a startup component which can be accessed from the FPGA fabric and this should be the selected internal clock signal. See the manual for your Startup component for more details

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