What is the difference between
>>> in verilog/system verilog? I know that
== tests for only 1 and 0, while
=== tests for 1, 0, X, Z. So how is that similar to the shift operator?
It is not similar to
===, if the left hand operand is signed then
>>> performs sign extension.
reg signed [9:0] b = 10'sb11_0101_0101; reg signed [9:0] a_signed; reg [9:0] a_unsigned; always_comb begin a_signed = b >>> 2; a_unsigned = b >> 2; end
#a_signed 1111010101 #a_unsigned 0011010101
Example on EDA Playground.
According to IEEE1800-2012
>> is a binary logical shift, while
>>> is a binary arithmetic shift.
Basically, arithmetic shift uses context to determine the fill bits, so:
- arithmetic right shift (
>>>) - shift right specified number of bits, fill with value of sign bit if expression is signed, otherwise fill with zero,
- arithmetic left shift (
<<<) - shift left specified number of bits, fill with zero.
On the other hand, logical shift (
>>) always fill the vacated bit positions with zeroes.
a = 5'b10100; b = a <<< 2; //b == 5'b10000 c = a >>> 2; //c == 5'b11101, 'cause sign bit was `1` d = a << 2; //d == 5'b10000 e = a >> 2; //e == 5'b00101