While routing my CY7C68013A based PCB I just realized that regular USB B receptacle and mini USB equivalent have D+ and D- effectively swapped.

It seems that the chip was prepared for regular size receptacle (DP is on the left if looking towards the chip), while for mini USB I have to route one of the tracks under the receptacle.

Is it really like this, or did I mess something up? How am I suppose to keep the tracks impedance and length constraints, while one of the tracks needs to go a different way, around the receptacle pads?

  • \$\begingroup\$ Most likely getting impedance and length matching perfect on those lines wont make that big of a difference, especially if the lengths aren't too different. I would like to see what a "professional" has to say though. \$\endgroup\$
    – Kellenjb
    Apr 20, 2011 at 14:13
  • \$\begingroup\$ Which encapsulation (package) are you using? \$\endgroup\$ Apr 20, 2011 at 14:24
  • \$\begingroup\$ For the connector? It's something like this: farnell.com/cad/452550.pdf The chip itself is TQFP-100 version. \$\endgroup\$ Apr 20, 2011 at 14:33
  • \$\begingroup\$ Be careful when you're laying out this part. Do not run traces underneath, between the mounting lugs, because the metal is sharp and can scratch through the solder mask. \$\endgroup\$
    – markrages
    Apr 20, 2011 at 15:23
  • \$\begingroup\$ The USB Spec is Extremely conservative. I've done some horrible things to USB cables, and still managed to run full USB 2.0 over them. \$\endgroup\$ May 7, 2011 at 5:58

3 Answers 3


I've noticed the same problem when routing boards with the FTDI FT232 chips. Here's what the CY7C68013A datasheet says about routing those signals:

  • DPLUS and DMINUS trace lengths should be kept to within 2 mm of each other in length, with preferred length of 20 to 30 mm.
  • Maintain a solid ground plane under the DPLUS and DMINUS traces. Do not allow the plane to split under these traces.
  • Do not place vias on the DPLUS or DMINUS trace routing.
  • Isolate the DPLUS and DMINUS traces from all other signal traces by no less than 10 mm.

I would suggest the zig-zag method, but only if it that little detour around the pin added more than 2 mm to the trace length.

  • 2
    \$\begingroup\$ FT232 chips are full-speed devices, running at a maximum of 12 Mbit/s. The Cypress chip referenced is a USB 2.0 High-speed device, which can do up to 480 Mbit/s. The routing requirements are similar (at least they're both using differential signals), but they won't be identical. \$\endgroup\$ May 5, 2011 at 14:47
  • \$\begingroup\$ Sorry, I didn't make it clear that those recommendations are from the datasheet for the CY7C68013A that the OP is using. I don't think the FT232 datasheet has such strict requirements, as you suggested. \$\endgroup\$
    – ford
    May 6, 2011 at 2:38

Are you sure that D- and D+ are swapped? I checked the USB2 specification. ECN 1 describes the miniB connector, and I see the same order for the regular and the mini: Vbus, D-, D+, Ground.

If the connections are swapped, can't you add a few zigzags in the shorter trace to make it as long as the other? (I don't think it is really necessary, but it might give you some rest :-))

enter image description here

  • \$\begingroup\$ Pins appear swapped at the PCB level, not at the plug level, due to different receptacle geometry - unless I've messed it up :) \$\endgroup\$ Apr 20, 2011 at 14:58
  • \$\begingroup\$ @Czajnik, could it be that it's intended to be mounted on the bottom of the board and someone is just tricking it? \$\endgroup\$
    – kenny
    Apr 20, 2011 at 15:45
  • \$\begingroup\$ I guess not, as PCBs with components on one side are obviously cheaper to manufacture. The receptacle I want to use is a standard, commonly used component. Perhaps the perfect impedance and length match is not as critical as I think? \$\endgroup\$ Apr 20, 2011 at 19:15

This one docs states that the prefered mounting for microusb-b is on the underside. http://portal.fciconnect.com/Comergent//fci/drawing/10103593.pdf

I also had the problem when mounted on the topside that D+ D- would not line up. Had to put the chip below the connector instead and run the traces between shield pins.


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