3
\$\begingroup\$

I don't understand these sentences from Razavi's book, Design of CMOS Integrated Analog Circuit,

'the gate polysilicon and the source and drian terminals are typically tied to metal(aluminum) that serve as interconnects with low resistance and capacitance. To accomplish this, one more "contact window" must be opened in each reigon, filled with metal, and connected to the upper metal wires'.

Does this mean that one and more "contact window" could lead to low resistance and capacitance, if it is, how could it be?

\$\endgroup\$
  • \$\begingroup\$ What page number? \$\endgroup\$ – Adam P Apr 22 '11 at 14:34
  • \$\begingroup\$ @Adam: it is 28 in my book, but i'm using the english edition published in China, so it maybe a little difference there. \$\endgroup\$ – Jichao Apr 23 '11 at 0:38
2
\$\begingroup\$

enter image description here

A "contact window" is a loop that connects two materials (usually a metal and a semiconductor) together. Since they are square frames, they look like windows. The picture above is a two-gate mosfet with metal gates. For each of the three source/drains you can clearly see the contact windows, connecting the semiconductor islands to the metal pads. The gates do not need a contact windows in this particular design, as they are already made out of metal.

What leads to lower resistance and capacitance is not so much the contact window itself, but the fact that the signal travels the distance through metal instead of semiconductor.

\$\endgroup\$
0
\$\begingroup\$

Each window has a significant resistance (may go as high as 10 Ohm). So in order to minimize losses on the contanct windows, many of them are put in parallel. There is a trade-off here though: each contact also has a capacitance and when you put them in parallel you add the capacitances.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.