I don't understand these sentences from Razavi's book, Design of CMOS Integrated Analog Circuit,
'the gate polysilicon and the source and drian terminals are typically tied to metal(aluminum) that serve as interconnects with low resistance and capacitance. To accomplish this, one more "contact window" must be opened in each reigon, filled with metal, and connected to the upper metal wires'.
Does this mean that one and more "contact window" could lead to low resistance and capacitance, if it is, how could it be?