Say you have a digitizer that's converting an analog signal and feeding it to a microprocessor for whatever you'd like to do to it. How would increasing the number of bits of the digitizer affect the signal? I feel like it would have something to do with the resolution of the signal but that's just a guess and I have no idea how to explain this concept. Also, I feel like there should be a mathematical relationship between these two but I don't think I've seen it anywhere else online.

Additionally, how would the sampling frequency that was first used to obtain the analog signal be related to the number of bits. Are there any precautions that should be taken?

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    \$\begingroup\$ Do you mean to increase the number of bits in the 'digitizer'? Increasing the number of bits in a ADC increases the number of bins a value can fall in to; the resolution increases. But the microprocessor reading that digitized information has no effect on its resolution. \$\endgroup\$ – Samuel Oct 12 '14 at 23:36
  • \$\begingroup\$ Yes! Sorry I will edit. \$\endgroup\$ – farid99 Oct 12 '14 at 23:40
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    \$\begingroup\$ A great presentation on the technical aspects of ADCs - very much worth a read: unirioja.es/cu/lzorzano/ABCs_of_ADCs.pdf \$\endgroup\$ – Majenko Oct 12 '14 at 23:45

Whenever a continuous signal is encoded into a finite number of bits, there will be some quantizing noise. This is the error introduced because not all possible input values can be accurately represented by the digitized signal. For example, assume that an analog signal ranging from 0V to 5V is digitized using a 2-bit ADC. Using equal step sizes, this might be done as shown in the table below: $$ \begin{array}{cccc} {\bf voltage} & {\bf binary} & {\bf code} & {\bf output} \\ 0 \le v < 1.25 & 00 & 0 & 0.0 \\ 1.25 \le v < 2.50 & 01 & 1 & 1.25 \\ 2.50 \le v < 3.75 & 10 & 2 & 2.50 \\ 3.75 \le v < 5.00 & 11 & 3 & 3.75 \\ \end{array} $$

If voltage of 2.0V is digitized, it is encoded as 01 binary, but so would voltages of 1.26V or 2.48V. If we convert back to analog, all of them would result in an output voltage of 1.25V according to the scheme above. The difference between the sampled voltage and the corresponding output is quantizing noise.

It's easy to see that adding bits adds resolution and reduces quantizing noise.

As for sampling frequency, there is a thing called the Nyquist-Shannon sampling theorum that states to be able to successfully reproduce any digitized signal, one must sample at no less than twice the highest frequency you wish to reproduce from the input. This is independent of the number of bits one uses to digitize.

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    \$\begingroup\$ Well put, but Nyquist limit only gives the condition to avoid frequency aliasing (e.g. 1.25kHz signal sampled at 2kHz is indistinguishable from a 0.75kHz signal due to frequency aliasing). But with only 2 samples per cycle, there can be large errors in amplitude, offset, and phase. What happens if those two points occur at 0 degrees and 180 degrees? 100% amplitude error. To fully reconstruct a sinewave with reasonable quality, requires at least 6-10 points per cycle. So if you want to capture and reconstruct a 1kHz sinewave, sample rate should be at least 10kHz or more. \$\endgroup\$ – MarkU Oct 13 '14 at 1:56
  • \$\begingroup\$ @MarkU actually you only need a very small fraction over 2x to exactly reconstruct a sine wave's frequency+amplitude (in theory 2.0001x works, but to avoid noise something like 2.5x is usually used). However, reconstruction will then involve using an FFT, zero-padding, and inverse FFT. \$\endgroup\$ – helloworld922 Oct 13 '14 at 4:21

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