I'm working on modeling a circuit implemented on an FPGA, and the fundamental question I keep running into is this: what is a logic element? I need to be able to model the temporal response of the output when the input changes as accurately as possible. Right now we are using a simple RC circuit driven by a binary voltage source (corresponding to the implemented logic function) with a time constant of ~400 ps, but clearly that's too simplistic and it's not accurate enough.
Looking at e.g. the Altera handbook, LEs are implemented essentially as a look up table with routing components around it. Can someone point me in the direction of (a) a circuit diagram of one of these look up tables or (b) a more appropriate modeling framework? I'm new to this, so please be gentle.