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Reading a presentation on an MPU evaluation board I found this particular circuit:

back powering prevention on JTAG

Can someone please explain me the logic behind this and what is this "back powering" scenario that the presentations talks about?

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Back Powering is what happens when data entering an un-powered device's input pin is routed up through the internal ESD diodes in the device onto its power rail. This often provides enough power to run the device (escpecially with idle-high signals coming in) but with (often dire) consequences.

  • ESD diodes may burn out
  • IO pin circuitry may be damaged
  • The device providing the errant signals may be damaged

It's hard to tell from that circuit, but I have to assume (due to a process of deduction) that it is in the evaluation board, not the JTAG device.

There are three important power circuits in question here - REG_3V3, the power from the internal voltage regulator, VDDIO_3V3, the JTAG IO port 3.3V power signal, and WALL_5V_IN, the main input power to the board.

The op-amp compares those voltages (actually it compares VDDIO_3V3 to 87% of REG_3V3, thanks to the voltage divider R298 and R306). If VDDIO_3V3 is above that 87% reference voltage, then the output of the op-amp is high. That high signal will enable the MOSFETs in the data path to allow the signals through the interface.

However, when there is no power to the board, and when the JTAG is plugged in and powered, VDDIO_3V3 will be at 3.3V, and REG_3V3 will be at 0V, so you would expect the output of the op-amp to be high. But, we're forgetting WALL_5V_IN. As there's no power to the board, that will also be at 0V, so the op-amp will be unpowered. Therefore it doesn't output anything at all, and the voltage divider formed by R297 and R305 between 0V and GND would pull the output into a low state. That then turns off the MOSFETs isolating the JTAG bus from the rest of the board, protecting it from any signals coming in that could damage it.

As for why there's a comparator in there, and not just monitor the incoming power directly by tying it to the gate of the MOSFETs? The user manual explains it as thus:

The signal lines are disconnected when the i.MX28 shuts down to prevent back powering from the JTAG tool into the i.MX28 processor. The disconnect circuit is triggered by the falling edge of the VDDIO_3V3 supply via comparator U48 when the i.MX28 processor shuts down.

The VDDIO_3V3 supply is generated internally inside the i.MX28 controller. It is possible (by the sounds of things) for the board to be powered up (WALL_5V_IN == 5V, REG_3V3 == 3.3V) but for the chip to be shut down and not running (VDDIO_3V3 == 0V), in which case the MOSFETs should be in an off state - hence the comparator to compare the 3.3V generated by the i.MX28 with the externally regulated 3.3V supply.

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  • \$\begingroup\$ But the parasitic diodes inside a MOSFET can have drop of about 1.5V, I would have bet this goes against some specification.... So when you say "when there is no internal power" do you mean the board is being powered from the JTAG? I don't see why to use the JTAG if nothing is being powered :P \$\endgroup\$ – mFeinstein Oct 13 '14 at 23:39
  • \$\begingroup\$ Aren't these JTAG lines inputs? How would they give any back power? Unless the pins can be configured to be regular IO right? \$\endgroup\$ – mFeinstein Oct 13 '14 at 23:43
  • \$\begingroup\$ And which is the "JTAG power connection" you speaks about? Which pin should I be looking for in this diagram? \$\endgroup\$ – mFeinstein Oct 13 '14 at 23:44
  • \$\begingroup\$ Let me just re-phrase my answer now I'm not both tired and somewhat inebriated. \$\endgroup\$ – Majenko Oct 14 '14 at 8:58
  • \$\begingroup\$ I have now managed to really confuse myself over this circuit. Is it in the evaluation board, or in the jtag programmer device? \$\endgroup\$ – Majenko Oct 14 '14 at 9:30

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