# How do you reduce an 8 output ALU to a 4 or 3 output ALU?

I can implement the functions in the picture below, but then if I implement them independently, I would have 8 outputs to the mux. Our professors wants us to reduce the ALU to only 3 or 4 outputs, I have tried but am not getting anywhere?

• Please elaborate on what you tried. Oct 15, 2014 at 3:21
• Hint: What's the difference between 6 and 7? Between 3 and 5? Between 4 and 5? Oct 15, 2014 at 3:25
• the difference btw 5 & 7 is that they are opposites, diff btw 3&5 is that one is subtraction and the other is anding. 4 and 5 are oring and anding, but i don't see how to use these differences. i can only use xnor and xor because they are opposites, but the rest i can't see Oct 15, 2014 at 4:09
• Have you learned about De Morgan yet? Oct 15, 2014 at 4:28
• 4 & 5 are quite the same except that one is inverted. relating 3 and 5 in demorgan is quite confusing Oct 15, 2014 at 5:11

Addition and subtraction have inverted constants $C_{in}$, we can be connected to $(I_3 \vee I_4)$. Then invert the subtracting value before passing to a full adder. ADD/SUBR/SUBS can be expressed as :

$$(R \forall I_3) + (S \forall I_4) + (I_3 \vee I_4)$$

Using the same xor inversion method you can mearge:
AND/NOTRS : $(R \forall I_3) \wedge S$
EXOR/EXNOR : $R \forall S \forall I_3$

This make 4 possibilities that can be decoded using three 2-to-1 muxes. simulate this circuit – Schematic created using CircuitLab

Hint: Gate count can be reduced further by share logic with the gates inside the fulladder.

• thhankyou very much, this is very very helpful Oct 18, 2014 at 2:02