# ISA efficiency code compaction and memory traffic

I'm having issues understanding this problem and am new to ISA's. Here's a problem with 3 questions and my biggest question is, what is supposed to happen? Specifically, the HLL Code at the bottom.

Assume four ISAs

1. accumulator-based
2. stack-based
3. memory-to-memory (operands located in main memory)

Instruction / data size

• all data operands 4 bytes
• all memory addresses are 16 bit
• all opcodes 1 byte
• memory address fields 2 bytes wide
• register fields in load/store machine are 4 bits wide (16 32-bit registers)

Additionally, all memory addresses are 32-bits long and all instructions and data are fetched in one single memory access in the case of memory-memory architecture, no need to use additional memory location.

Compile code for four ISA's and determine the metrics: 1) code size 2) data memory traffic, including addresses, 3) instruction traffic, including addresses.

HLL code:

 A = B + A
C = A - C + D

• What have you tried so far? Also, your specifications are inconsistent. One bullet says that addresses are 16 bits, while another says they're 32 bits. Oct 15, 2014 at 14:44
• @DaveTweed it does seem inconsistent but it's taken word for word from a book I'm trying to get through. Is it possible that there are two types of memory addresses? I rephrased it a bit. So far I've created a table for the four ISA's with 3 rows (code size, data traffic, instruction traffic). Oct 15, 2014 at 14:52
• This is clearly a question that depends on all of the material that came before it in the book. They presumably discussed the key characteristics of the four ISAs listed in this question. Your task is to come up with a reasonable sequence of instructions for each of the ISAs that implements the HLL functionality specified, and then analyze the memory access patterns of each of those sequences. As it stands, the question is far too broad to answer here. Do you have a specific point or concept that is giving you trouble? Oct 15, 2014 at 15:15

As a hint to get you started, here are some possible instruction sequences for the first HLL statement:

Accumulator-based

load A
store A


Stack-based

load A
store A


add B, A


Register-based

load A, r1
store r1, A


Your job is to figure out how big each instruction is, and also what the memory access patterns are for both instruction and data operations as each sequence executes.