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I have an inverting integrator

enter image description here

that integrates the input signal (green) into the blue signal.

enter image description here

If I do nothing, the integrator output will go down and down and down... I don't want this. I want to reset my integrator back to ~9V when the second green pulse comes.

With some knowledge in digital circuit, I already produce the "switch signal" (green narrow pulses) as shown below.

enter image description here

Finally, I need to build a switch circuit that resets the integrator (basically C1) every time it sees the green narrow pulse. How could I build this switch circuit?

My Attempt

I tried using an npn BJT who is on when V_{BE}>0 and V_{BC}>0. However, this is not working, maybe because my green pulse is only 1V (from digital circuit) and the integrator output is as high as 9V. There is no way whereby V_{BE}>0 and V_{BC}>0. Also, I feel this way, the switch circuit is somewhat "disturbing" the integrator.

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4 Answers 4

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Funny but it seems like a very similar question has been asked just recently, and a piece of a circuit I've used before may help you too. This would be my approach.

Integrator with auto reset

You would have to set the voltage divider resistors at the (+) input of the left OP amp so that the input pulse would cross the threshold. If you think the pulse will be less than perfect, you might also want to experiment with an high added resistance to offer some hysteresis. When the pulse goes high, the output of that first OP am will quickly switch low, and the output of the integrator will begin to rise slowly over time. When the pulse goes low, however, its output will quickly switch high, and the output of the second OP AMP will drop almost immediately, like a RESET. This is due to the much lower resistance (and hence shorter) integration timing for the RESET case. You can reverse the action to behave like your version by switching the twodiode resistors, putting the voltage divider on the (-) input of the first OP AMP, and feeding your input to its (+) input through an additional resistor. The important thing is that now you'll have a RESET after each pulse event. If you were sampling the output of the second OP AMP, and saving the highest result recorded every time the pulse went low, you will a have a good measure of the pulse duration. In addition, I'd argue that resetting AFTER the event is always better than resetting at the start of the event. The reason is that any reset is likely to take a short but still non-zero amount of time. So resetting AFTER the accumulation ensures that any reset time does NOT corrupt your pulse duration measurement.

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  • \$\begingroup\$ Thanks a lot. The interesting thing is the signal that I need is actually from the - pin of the right op amp, instead of its output pin. This is weird. Also, the reason why I wanted to reset at every pulse's start instead of the end is that I wish to show the value on LED for a period of time. What you said totally makes sense. But seems that I need another small circuit to latch the peak so as to be shown for a period of time on LED. \$\endgroup\$ Oct 16, 2014 at 3:02
  • \$\begingroup\$ What if I insist discharging the integrator at the start of a hump? How should I modify yours design? Thanks! \$\endgroup\$ Oct 16, 2014 at 5:01
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    \$\begingroup\$ Just remember that you can't reset in zero time. So if you insisted in resetting at the start of the pulse, you would first have to decide how much time and precision you're willing to sacrifice. Wouldn't it be better to add maybe a simple one gate DELAY circuit in the path between left OP-AMP out and the top diode? Then, between the time the pulse ends and the time delay expires, OP-AMP-2 will HOLD its output, giving you time to "READ" it. I'm new to this forum and am not sure how to add an additional circuit to a comment, but maybe what I've suggested already will help? \$\endgroup\$
    – Randy
    Oct 16, 2014 at 14:03
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First things first, you haven't shown the full circuit. The full circuit of a resettable integrator has a resistor on the input like this: -

enter image description here

Without the input resistor the capacitor will charge at a rate determined by the output impedance of the op-amp and not in a controlled manner unless you are injecting a current into the input but I can see you are not because your green traces are indicating against a scale of voltage on your graph.

Note that there is also shown a switch across the capacitor to discharge it or "reset" the integrator and this is the key to perhaps what you want to achieve. If this suits your requirements, try using an analogue ("analog" for west of the Atlantic ocean) switch - it contains FETs that can be controlled digitally to short out the capacitor very quickly.

Here is also a useful tutorial on integrators.

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Integrator with reset

The discharge current through the transistor is limited by the hFE of the transistor.

EDIT

Showing base and collector currents during reset action. The current flowing in R1 has been omitted as it is very small compared to Ic. Integrator during reset action

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  • \$\begingroup\$ It is interesting to show where Q1's base and collector currents flow... \$\endgroup\$ Apr 9, 2020 at 9:49
  • \$\begingroup\$ Thanks for the edit. I still wonder if the base current flows through C1 (as shown in the second picture) or through R1... \$\endgroup\$ Apr 9, 2020 at 17:33
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    \$\begingroup\$ I wondered that for a while also. I decided that if the base current flowed through R1 then the voltage at the op amp's inverting input would have to rise which would make the output go a little more in the negative direction bringing the inverting input back to (almost) the same voltage as the non-inverting input forcing Ib to be part of the capacitor's discharge current and flow into the op amp's output. Seems reasonable. \$\endgroup\$
    – James
    Apr 9, 2020 at 17:46
  • \$\begingroup\$ I tend to accept your explanation because the total voltage (0.9 V + VC2) exceeds the op-amp output voltage so the base current should enter the op-amp output. \$\endgroup\$ Apr 9, 2020 at 17:55
  • \$\begingroup\$ Is it correct to apply 9 V to the op-amp output (in the third picture)? \$\endgroup\$ Apr 10, 2020 at 7:39
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enter image description here

You can use this example as integrator discharger. D2.4 is a gate from a 4066 and Q2 a 5V pulse.

Enjoy!

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    \$\begingroup\$ Unfortunatly there is no explanation in your answer! Try elaborating more about why you think your example might be a godd solution, otherwise this answer is likly to be deleted. \$\endgroup\$
    – jusaca
    Apr 9, 2020 at 6:50

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