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Often in digital systems when multiple components communicate with each other they use strobe signals. Among these are data and address strobes. The strobe signal being asserted means that the data or address is ready to be latched. However, the actual latching takes place only on the edge as the strobe signal is deasserted.

In sequential circuits a clock signal is used to latch data in the registers. How does this strobe signal relate to the clock? Is it actually fed into the clock port of the registers perhaps after inversion to match the edge with what is required by the register to latch data?

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In clocked systems, the "strobe" signal is treated as an "enable" signal for the corresponding latch or register. In other words, the data is captured on any clock edge for which the strobe or enable is active. This means that the timing is strictly relative to the clock edge, but the strobe indicates which clock edges are relevant.

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  • \$\begingroup\$ In the earlier days we had latches which are level triggered, a strobe signal would make complete sense with that. The strobe signal stays asserted for a great many clock cycles, you mentioned that it is only treated as an enable signal and data can be latched on any clock edge when strobe is asserted. Nowdays we have flip flops instead of latched, why does the strobe signal remain asserted for so many clock cycles then? If it goes low just for one or two clock cycles, that is still enough to latch the data right? \$\endgroup\$ – quantum231 Oct 16 '14 at 18:35

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