Why are All DDRs' (DDR, DDR2, DDR3) Internal Clock Set to 200MHz?

Question

If we see the DDR Upgrade technology explain below the internal clock of all DDR is set to 200 MHz.

DDR

For example,DDR-400

Efficient frequency data bus is 400 MHz

True clock rate (IO buffer frequency) is 200 MHz

Internal clock rate of DDR memory is 200 MHz

So In order to transfer 1 bit per clock (via each data line) along the external bus operating at the effective clock rate of 400 MHz, 2 bits must be transferred per clock of the internal 200 MHz data bus.This data access scheme is also known as 2n-prefetch.

DDR2

DDR2-800 memory chips Efficient frequency data bus is 800 MHz

IO buffer frequency is 400 MHz

Clock rate of the internal data bus is just 200 MHz

So in order to transfer 1 bit (via each data line) per clock of the external data bus operating at the efficient clock rate of 800 MHz, 4 bits must be transferred per clock of the internal 200 MHz data bus.So this data access scheme is also known as 4n-prefetch.

DDR3

DDR3-1600 memory chips Efficient frequency data bus is 1600 MHz

IO buffer frequency is 800 MHz

Clock rate of the internal data bus is just 200 MHz

So in order to transfer 1 bit (via each data line) per clock of the external data bus operating at the efficient clock rate of 1600 MHz, 8 bits must be transferred per clock of the internal 200 MHz data bus.So this data access scheme is also known as 8n-prefetch.

Now Here is my question

1. For increasing the data Bus speed why can't we increase the internal clock?

2. If we increase the internal clock what are the consequences can be faced?

Answer 1

A DDR memory device actually consists of two distinct components:

1: A series of memory arrays composed mostly of capacitors, which are written to and read from using a very wide bank of differential amplifiers. This is fundamentally an analogue circuit, surprisingly enough.

2: An interface buffer, which allows the hundreds or thousands of individual bits produced by a single memory-array read cycle to be interfaced to a reasonable number of data lines to the Northbridge or CPU. Several cycles on the external interface are needed to transmit the data in the buffer.

In general, the feature size of semiconductor technology decreases over time as manufacturing technology is refined. This has different effects in the above two components.

For the memory array, the differential amplifiers become more sensitive and the individual capacitors become smaller. This allows a larger array to be constructed in the same die area, reading out more bits per cycle. The speed of the array remains roughly the same, however.

For the interface buffer, some of the data paths become shorter and therefore faster, required voltage swings reduce, and there is now space for better skew-correction, clock recovery, etc. This permits higher external signalling speeds within a reasonable power and area budget. The original DDR RAM simply transmitted data on both the rising and falling edges of the clock signal, instead of only on the rising edge as SDRAM did. More recent versions effectively multiply the basic clock signal as well.

This "basic clock signal" usually works out to around 200MHz in mainstream products of each generation, though faster and slower devices are also available. In original DDR, a 200MHz clock meant 400 MT/s, and was often described as 400MHz (or DDR-400) though the highest frequency signal is actually 200MHz. In DDR2, the basic clock is doubled using a PLL at both ends of the interface, so the actual clock rate is 400MHz and there are 800 MT/s. In DDR3 the clock is quadrupled and in DDR4 it is octupled, giving typically 3200 MT/s today. As you can imagine, the timing relative to the clock edges has to be controlled very carefully.

Since the memory arrays themselves haven't changed much in speed, these higher interface speeds come with increased "column strobe latency" (CL) figures. These describe how many transfer cycles elapse between providing the address and receiving the data, and are used to accommodate the limited speed of the memory arrays relative to the interface bus.

One of the things that the basic clock controls more-or-less directly, rather than through a PLL, is the self-refresh cycle of the memory arrays. Using capacitors to store bits is very space-efficient, but the charge leaks out of them rather easily and weakens the indication within a few tens of milliseconds, so the memory arrays must constantly cycle through their contents, reading and re-writing them to ensure they remain valid.

Answer 2

Because DDR is about the memory device's external interface, only and only about it.

Internally, SDR SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, and DDR4 SDRAM have (nearly) the same dynamic memory array built around capacitors and distinct in the silicon responsible for the interface (it consumes a significant part of the overall chip area) and in the volume of such the array.

As for up to today, the dynamic memory devices evolved in interface throughput (Gbps), manufacturing process (nm), rail level (Volts), power consumption (Watts), but not in the speed of the internal array, i.e the memory itself, which is kept (nearly) the same beginning from SDR SDRAM.

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Update (from here):