# An Explanation of CMOS Logic

While trying to understand CMOS Logic on Wikipedia for class, I came upon this paragraph which I can't quite wrap my head around on the duality of CMOS:

An important characteristic of a CMOS circuit is the duality that exists between its PMOS transistors and NMOS transistors. A CMOS circuit is created to allow a path always to exist from the output to either the power source or ground. To accomplish this, the set of all paths to the voltage source must be the complement of the set of all paths to ground. This can be easily accomplished by defining one in terms of the NOT of the other. Due to the De Morgan's laws based logic, the PMOS transistors in parallel have corresponding NMOS transistors in series while the PMOS transistors in series have corresponding NMOS transistors in parallel.

Specifically, what does it mean that "All paths to he voltage source must be the complement of those to the ground"?

And how is this accomplished by defining one in terms of the NOT of the other?

Any explanation would be greatly appreciated, and if you can provide a simple example of this even better.

• In digital logic, transistors act as switches. Commented Oct 16, 2014 at 5:39

It's actually quite simple, and it's based on two requirements:

1. Every node in the signal path must be connected to either Vcc or GND, to be at logical level 1 or 0 respectively;

2. There should never exist a conductive path between Vcc and GND, else it will short the supply and start draining a lot of current and possibly burning some parts here and there.

Therefore you must make sure that if the pull-up network is conducting, the pull-down is not. Hence their logical function must be the opposite.

• I believe VCC and Gnd do short during transitions for a very small amount of time. It is this shorting that contributes to the current draw, otherwise, CMOS logic has very low current draw. Commented Oct 16, 2014 at 6:03
• It's not that they short but rather that both transistors are partially conducting. However the largest power drain is the continual charging and discharging of the gate capacitances. This is why power consumption of CMOS digital devices goes up as switching frequency increases. Commented Oct 16, 2014 at 6:13

It might be easier to see this with an example. Let's take a look at the CD4001/CD4011 gates which are NOR or NAND gates respectively. Here is the internal schematic of a single NOR gate and a single NAND gate from the datasheet:

You can ignore the four transistors that form the buffer for the output:

Now for the NOR gate you can see that there are two P-channel MOSFETs in series to drive the output (buffer input) high when both inputs are low. There are two N-channel MOSFETs in parallel to drive the output (buffer input) low when either input is high.

The two sets of transistors are never on at once, so the current drain is just leakage under static conditions and there is always a low impedance since either one or the other of the N-channel transistors is on, or both of the P-channel transistors are on.

The situation is flipped for the NAND gate (the lower schematic) with two P-channel transistors in parallel and two N-channel transistors in series.

• I don't love that MOS symbol, it's quite a lot of traits for just one transistor Commented Oct 16, 2014 at 8:28
• @clabacchio Yes, the information on the substrate connection kinda clouds things for the purposes of this discussion. It's useful in understanding things like transmission gates which are just one step beyond this though. Commented Oct 16, 2014 at 8:31