I am now confused by one piece of Verilog Codee, its kind of testing the blocking or non-blocking assignment features that combination with Delay model.
module cl_tb; reg x,y,z; initial begin x = 2; #4; y <= #9 x; x = 1; #50 $stop; end initial begin $monitor("%0t,%d,%d,%d",$time,x,y,z); end always @(x,y) begin z = # 2 x+y; end endmodule
By hand-calculation, I could get the result [ Time: X value, Y value, Z value] below: [0: 2,x,x] [2: 2,0,2] [4: 1,0,2] [6: 1,0,1] [13: 1,2,1] [15: 1,2,3]
However, the simulation result is [0,0,x,x]; [4,1,x,x]; [13,1,0,x]; [15,1,0,1];
Which you can see from the link http://www.edaplayground.com/x/Was
I am wondering why the always@(x,y) was not triggered at timeslot 2 and 4.