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I'm implementing a radio in Verilog. the time taken for bit reversal while computing the FFT is more. it is almost equal to a symbol time (OFDM system). Can I use a FFT library in C, which can be integrated to the code, to speed up my simulation?

If so, can these codes be used for an FPGA in real time?

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  • \$\begingroup\$ Note: you should not expect to be able to run the simulation in anything even close to real-time. \$\endgroup\$ – pjc50 Oct 17 '14 at 8:22
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Well, you might be able to do it for accelerating your simulation, but it is not possible to synthesize this and put it on an FPGA. Verilog code is a hardware description language that describes the functionality and interconnections of your design. It is not executed like a program, it is synthesized into the equivalent of a schematic diagram.

You could run your FFT algorithm on a CPU that's written in verilog, but that rather defeats the purpose of using an FPGA if you need a very fast FFT. However, there are FFT cores available, so you should not have to reinvent the wheel. I believe the Xilinx core generator can generate one, or you can use one from a site like opencores.org.

By the way, bit reversal, if I understand what you mean by that, should be a trivial operation on an FPGA if it's implemented correctly.

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I doubt this is possible.

Remember that when you are writing Verilog your are not programming. Your Verilog code will not "run" on your FPGA. Instead you are describing a logic system. This is different thing. One will run line after line is a sequential manner when the other describes a system where your thing are working in parallel.

Unfortunately the Verilog language looks like C but for me this is misleading because the fundamental behind is so different.

To answer your question, a piece of code that is meant to be run as a sequential program cannot be used efficiently here. There are some C to Verilog translator that tries to create description of what the C code does in Verilog. But for a complex library which will for sure do some memory allocation of dynamic things, this may not work at all. Why not looking for a FFT code directly? Such as what you can find at opencores.org?

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If you're just targeting simulation, then there are ways to interface languages like C/C++ with Verilog/SystemVerilog, such as Verilog Procedural Interface and System Verilog Direct Programming Interface

But AFAIK, I don't think the synthesis tools are smart enough to synthesize any of these C/C++ calls for an FPGA

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