9
\$\begingroup\$

I am working on a very spotty motor failure (I am not the designer). We have a wound armature which is switched by power MOSFETs. These are driven by a FET totem pole type FET driver. When the driver is off therefore, the gate of the power FET is floating. Yeah, I know. Bad design choice. I'm just cleaning up the mess.

There is a triac and drive circuit controlled by a micro output on the stator side of the motor. When you plug the motor in, the drive line is floating since the micro port is tristated until boot is complete. Since this port line is going into an AND gate and floating, you end up with about 5 cycles of AC on it of sufficient amplitude to fire the gate and this the triac. This puts about 3-5 half cycles of the line on the stator, with peaks of up to 100A depending on source impedance. Yup. Another design error - it should have been pulled down.

Problem - this does not happen often, nor does the power MOSFET failure. Out of hundreds of motors, we have had three fail with power FETs shorted drain and gate to source. Question - I am trying to decide if this series of current spikes (which do induce voltage onto the armature - and the turns ratio is 1:1) is a likely suspect, given the poorly designed power MOSFET circuit. The MOSFETs are right across the armature winding. When the motor fails, it does not fail during run. It seems to fail as soon as you plug it in. My evidence is all circumstantial - I have so far been unable to force a failure. But the massive spike at plugin, the rarity of the failure, and the difficulty of duplicating it seem to point at this. If I'm going down the wrong path, I need to know and know why. This seems like it may damage the FET, but I'm looking for path to failure here that makes sense.

At the moment I am cyling several motors, using a PLC to keep an eye on them. The plan is to cycle until failure, apply design corrections and run again. Unless I get a flash of genius.

\$\endgroup\$
  • \$\begingroup\$ Welcome to EE.SE. All in all, this is a pretty good first question. +1 from me. \$\endgroup\$ – Adam Lawrence Oct 17 '14 at 12:55
  • 3
    \$\begingroup\$ Further to the question - if I'm looking for a fault which I cannot replicate, and I find some 'badness' in there that makes me scratch my head, I would do what I could to fix that badness even if the root cause remains elusive. It sucks, but sometimes a rare, corner-case issue has to be fixed empirically, by making improvements and seeing if the failure rate over time and quantity improves. \$\endgroup\$ – Adam Lawrence Oct 17 '14 at 13:00
  • 2
    \$\begingroup\$ This is just speculation, but if you have a MOSFET with the gate floating, and you apply a pulse of voltage to the drain, drain-to-gate capacitance could cause the gate-to-source voltage to exceed the transistor's rating and create a permanent failure. \$\endgroup\$ – Dave Tweed Oct 17 '14 at 13:03
  • \$\begingroup\$ To first comment - we are a new company and hyper sensitive to field failures. I agree that this is a sensible course of action - fix the goofs and look at returns data. It's questionable if management will buy that but it's worth a shot. \$\endgroup\$ – Mike Lipphardt Oct 17 '14 at 13:12
  • \$\begingroup\$ To second comment, the capacitive coupling to gate is kind of freaking me out a bit too. That line should have been pulled down if for no other reason than ESD protection, but it would have protected against this failure mode too. I was thinking along those lines when I started the cyclic test program. Thank you. \$\endgroup\$ – Mike Lipphardt Oct 17 '14 at 13:14
2
\$\begingroup\$

FET gates MUST NOT float.
Nothing can be guaranteed in that state.

Miller capacitance will happily couple large drive signals onto the gate from drain transients. A gate driven above its Vgsmax value will often enough puncture the gate oxide and any combination of hard shorts between GDS can result. I have seen DS short with G open, GS short with D open, GDS all short and perhaps GD short with S open but I'd not be 100% sure of that.

For ANY power FET with an inductive load I add a GS zener mounted as close to the FET as possible, with a voltage rating above Vgs_drive_max and comfortably below VGS_abs_max. This transforms circuits which fail in minutes to hours into circuits which fail never.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.