I'm trying to get VGA working on my Altera DE0 board using Verilog, but haven't had much luck. It has the same pins as a normal VGA interface except red, green, and blue are all 4 bits each. Here is the logic I've been trying to use to get a solid color to display:
module solid_color (clk, vga_h_sync, vga_v_sync, R, G, B); input clk; output vga_h_sync; output vga_v_sync; output [3:0] R; output [3:0] G; output [3:0] B; reg [9:0] CounterX; reg [8:0] CounterY; wire CounterXmaxed = (CounterX==767); always @(posedge clk) if(CounterXmaxed) CounterX <= 0; else CounterX <= CounterX + 1; always @(posedge clk) if(CounterXmaxed) CounterY <= CounterY + 1; reg vga_HS, vga_VS; always @(posedge clk) begin vga_HS <= (CounterX[9:4]==0); // active for 16 clocks vga_VS <= (CounterY==0); // active for 768 clocks end assign vga_h_sync = ~vga_HS; assign vga_v_sync = ~vga_VS; assign R = 15; assign G = 15; assign B = 15; endmodule
When I try running it, I just get a message on the monitor saying that this display mode is not supported.
This is adapted from http://www.fpga4fun.com/PongGame.html. However, this version claims to be designed for 640x480 displays whereas my monitor is 1280x1024. Is this the issue? If so, how would I adapt this to fit the increased monitor size? (the clock I'm using is 50 MHz)
EDIT: I added in a clock divider module as follows to change the initial clock signal to 25 MHz:
module divide_clock_by_two(in_clk, out_clk); input in_clk; output out_clk; reg out_clk; always @(posedge in_clk) out_clk <= ~out_clk; endmodule
However, the monitor now just shows a black screen, no message about an incorrect mode.