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I've been reading about decoupling capacitors, and I can't seem to understand why ST recommends 100 nF decoupling capacitors on a 72 MHz ARM microcontroller.

Usually 100 nF decoupling capacitors are only effective up to about 20-40 MHz due to resonance. I thought 10 nF decoupling caps were more suitable since their resonance is closer to 100 MHz.

(Obviously, it depends on the package and its inductance, but those are just ballpark values from what I've seen.)

According to the STM32F103 datasheet, ST recommends 100 nF capacitors on VDD and 10 nF on VDDA. Why is that? I would think I should use 10 nF on VDD too.

ST Recommendation Capacitor Impedance

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  • \$\begingroup\$ How fast can you toggle the I/O on one of these devices. For sure it won't be at 72MHz. Note also the use of 10nF caps on more critical pins and also note the voltage regulator feeding the core. \$\endgroup\$
    – Andy aka
    Oct 19, 2014 at 19:12
  • \$\begingroup\$ What is "AVDD"? Do you mean "VDDA"? \$\endgroup\$
    – Peter Mortensen
    Jan 13, 2016 at 22:27

2 Answers 2

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Three things you should note:

1) Most bypass recommendations in datasheets and application notes are fairly random in my opinion. You may easily be a better engineer than the person who wrote the application note :-). A better datasheet would talk about how low an impedance you as a board designer should provide and to what frequency. I wrote about this here.

2) Most of the parasitic inductance comes from your mounting inductance (footprint and via length) and not the capacitor itself. This is why you would like a smaller package rather than a smaller value. This is also why you would want to get the vias close together and use closely coupled power/ground planes.

3) It's possible that the chip has some bypass as part of the package and die, but this should ideally be detailed in the datasheet before you can take advantage of it (back to my first point). If not (and this is likely), you can try to measure this yourself, like I show here.

You may want to use something like pdntool.com to select the best combination of bypass capacitors based on your impedance and frequency requirements. This method has worked reliably for many projects over the last 15+ years.

I excuse for plugging my own blog posts here, but it's just much faster for me to find the references I need that way. Feel free to ask more questions.

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    \$\begingroup\$ "1) Most bypass recommendations in datasheets and application notes are fairly random. " proof? do you have some secret inside knowledge of a global conspiracy to get people to use bypass caps wrong, promoted by "big - cap" companies. \$\endgroup\$
    – placeholder
    Oct 19, 2014 at 21:20
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    \$\begingroup\$ HaHa. Well you see stuff like "as close as possible". Is that solid engineering - or "fairly random"? To me a solid recommendation would talk about how low the impedance should be and to what frequency or something like that. As explained here: ee-training.dk/tip/good-pdn-low-impedance-to-infinity.htm \$\endgroup\$
    – Rolf Ostergaard
    Oct 20, 2014 at 7:49
  • \$\begingroup\$ Well I didn't have to read very far in that blog post "The even higher frequencies may actually be handled at the die level also, but this is not measurable at the board level as the interconnecting inductance on the package may be too high." which tells me enough. \$\endgroup\$
    – placeholder
    Oct 20, 2014 at 12:50
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    \$\begingroup\$ What did you this tell you? You are right - it's hard to measure this from the board level. But with no information about this in the datasheet it's also hard to justify designing anything based on the hope that it's there. \$\endgroup\$
    – Rolf Ostergaard
    Oct 20, 2014 at 14:36
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    \$\begingroup\$ I am basing this on experience from many different datasheets. I also recognize this may be more of an opinion than a fact I would care to prove, so I changed the wording in the answer to reflect that. You are entitled to another opinion. \$\endgroup\$
    – Rolf Ostergaard
    Oct 24, 2014 at 15:53
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The likely reason , and here I'm making an educated guess - since I did not design that chip, is that ST has incorporated some high quality by-pass caps on chip by using spare area on the die. This capacitance is very high quality, very high resonance and very tiny inductance. What is common is to use the gate, well and even metal layer capacitances, this reduces the off-chip capacitor requirements increasing a customer's likely hood of success.

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